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Observer
Observer
2,570 Views
Registered: ‎02-11-2016

SRIO Timeout in User Design

Hi! I'm working on a design with SRIO Gen 2 core, and one observation during our lab testing was that the IREQ port's ready signal from the core could go low for significant amount of time (100's of clock cycles) in the middle of an NWrite transaction. Unfortunately, in my design, I cannot afford to wait for that long, and I'll have to terminate this packet transfer and allow another master to access the bus. Is there any way I can gracefully end a packet transfer even if the last word was not sent (it doesn't matter if a few packets are lost, or the last NWrite fails)?

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Xilinx Employee
Xilinx Employee
2,474 Views
Registered: ‎05-01-2013

Could you just try deasserting "tvalid"?

When "tready" is ready again, assert "tvalid" and go back to work again. 

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Observer
Observer
2,455 Views
Registered: ‎02-11-2016

It's a little bit more than just deasserting tvalid. How do I cleanly break from the middle of a packet transfer? Say I'm transferring a large SRIO NWrite packet, and half way through the payload transfer, tready goes low for a long time. My source encounters timeout, and I stop trying to send the remaining payload. I want to start a new SRIO Nwrite when tready goes high next. Do I just start with a SRIO header just like that, or do I send one last packet (invalid data) with tlast high when tready goes high next. Would that stop the transfer and then continue on with the next valid data packet?

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Xilinx Employee
Xilinx Employee
2,436 Views
Registered: ‎05-01-2013

I believe that you should send one last packet (invalid data) with tlast high when tready goes high next.

If not, the new header may be considered as the data of the previous unfinished packet by the IP core.

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