Share MMCME2_ADV primitives in Aurora simplex and suplex channels (in the same quad)

[voco-mannheim]

Hi,

i need a 4-lane Aurora link between two Xilinx devices (Zynq XC7Z045 and Kintex 7) running at 4 x 10 Gbps, located in the same quad (same ref_clk). The back channel (Zynq -> Kintex 7) is not critical therefore i need 1 duplex and 3 simplex lanes to save ressources.

If i will setup this configuration in the Aurora IP core i must generate 2 cores (1 simplex channel with 3 lanes, 1 duplex channel with 1 lane). Unfortunately i need 2 MMCME2_ADV primitives for these cores.

Can i change the IP output to use only one MMCME2_ADV for both, the simplex and the duplex channels? The clock_module of the IP output use the tx_out_clk signal for the PLL input clock wich is provided from both IPs.

Are there restrictions to use such configuration?

Thank's

[venkata · Accepted solution]

Since you mention that Aurora should run at 10Gbps, I believe it should be Aurora 64B66B.

The configuration you mentioned is possible to use one MMCM if the line rate is same. You will need to generate one of the core with "Shared logic in core" and other with "Shared logic in example".

The core generated with "Shared logic in core" would provide the clocks (user_clk, sync_clk, refclk, qpll clocks, qpll lock etc.). You will need to connect these signals to the core generated with "shared logic in example".

[voco-mannheim]

Wonderfull!

Thnak's!