07-17-2014 06:47 AM
Hi,
i need a 4-lane Aurora link between two Xilinx devices (Zynq XC7Z045 and Kintex 7) running at 4 x 10 Gbps, located in the same quad (same ref_clk). The back channel (Zynq -> Kintex 7) is not critical therefore i need 1 duplex and 3 simplex lanes to save ressources.
If i will setup this configuration in the Aurora IP core i must generate 2 cores (1 simplex channel with 3 lanes, 1 duplex channel with 1 lane). Unfortunately i need 2 MMCME2_ADV primitives for these cores.
Can i change the IP output to use only one MMCME2_ADV for both, the simplex and the duplex channels? The clock_module of the IP output use the tx_out_clk signal for the PLL input clock wich is provided from both IPs.
Are there restrictions to use such configuration?
Thank's
07-17-2014 10:33 PM
07-17-2014 10:33 PM
07-17-2014 11:48 PM
Wonderfull!
Thnak's!