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Visitor rwmiller47
Visitor
2,729 Views
Registered: ‎08-03-2016

Timing Failure within AXI 1G/2.5G Ethernet Subsystem using VC709 development board

I am using the AXI 1G/2.5G Ethernet Subsystem Version 7 Rev 5 with the Vivado 2016.2 tools.  I am encountering a timing failure within the IP that does not seem possible.  I have connected 4 ethernet subsystems using one GTX block for SFP_sgmii operation.  I am getting several timing errors all related to the elastic buffer.  Within the elastic buffer there is one route that does not seem possible that is failing repeatedly.  I have attached a picture showing one of these errors.  The RAMD64E is driving a fanout of 1 and the destination is only a couple of cells away yet the net delay is greater than 7 nanoseconds.  I would not think it possible to get a routing delay on a single net on the Virtex 7 and I can't imagine that the IP does not work.  Any suggestions of where I should look to resolve this?timing failure.PNG

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Xilinx Employee
Xilinx Employee
2,673 Views
Registered: ‎02-06-2013

Re: Timing Failure within AXI 1G/2.5G Ethernet Subsystem using VC709 development board

Hi

 

Can you attach the core xci file and detailed timing report of the failing paths.

 

Do you see any critical warnings about constraints delivered with the core being ignored

Regards,

Satish

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Visitor rwmiller47
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2,663 Views
Registered: ‎08-03-2016

Re: Timing Failure within AXI 1G/2.5G Ethernet Subsystem using VC709 development board

Satish

Thank You for your response.

The only XCI files that I have are for each individual IP established within the design.  There are three sub ip's connected with the AXI 1G/2.5G Ethernet subsystem.  I have attached the XCI file for the PCS/PMA core which contains the failing signals. And the Ethernet subsystem xci.  I only see 1 critical warning for the AXI memory interconnect telling me that it expects at least one endpoint on a system generated xci for auto_cc_8_clocks.  I don't see any critical warnings about the Ethernet cores.  One additional piece of information.  I am not seeing any timing issues with Ethernet_0 which contains the shared logic within the core.  The 3 instantiations that share the resources from core 0 are the ones with errors.  I have used the auto connection in the block design.  I have attached an additional image here showing a route from a LUT to the register in the next column over which is shown as taking 7.237ns.  I guess I would like to know if anybody has connected 4 Ethernet subsystems using 2016.2 Vivado tools using one GTX block.  Do I have a tools set issue or could one of my files be corrupted.  This slow timing on a Vertex7 just does not make sense.

timing2.PNG

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Visitor rwmiller47
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2,639 Views
Registered: ‎08-03-2016

Re: Timing Failure within AXI 1G/2.5G Ethernet Subsystem using VC709 development board

OK I think this is resolved.  The AXI 1G/2.5G Ethernet Subsystem does not contain the constraints required for the IP to be implemented.  There is an Asynchronous clock boundary within the elastic buffer.  This clock boundary will never not be flagged as a timing violation.  The system thinks it does not have hold time sufficient between writes into the buffer and reads out of the buffer.  The routing then is made extra convoluted trying to increase the hold time and it then fails the setup time which is again actually a false path error.  At least they included the Verilog code for the elastic buffer so I could work out what the timing issues involved were and what each meant.  By writing some constraints I was able to eliminate these false errors and get the timing to function.

 

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Visitor lyrfpga06
Visitor
2,461 Views
Registered: ‎07-23-2009

Re: Timing Failure within AXI 1G/2.5G Ethernet Subsystem using VC709 development board

Hello rwmiller47,

 

Can you, please, share the constraints you added to solve this issue? I have hold time violation for the elastic buffer that I could not solve on my own. I have two AXI Ethrnet subsystems. One core forwards its clocks to the other one (shared logic).

 

Thank you in advance.

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