08-28-2014 06:11 AM
I am using the Tri-Mode Ethernet MAC IP(v8.2) provided by Xilinx to transmit UDP packets via ethernet frame. I have modified the example design for AC701 board in Vivado 2014.2 to transmit UDP packets.
I was successful in transmitting continuous UDP packets of fixed size over the Ethernet interface by modifying the state machine of module axi_pat_gen_inst for this purpose.
But when i included a FIFO in my design as can be seen from the files i have attached as there needed to be a connection between a slow user clock & a fast axi_clk, i have started to drop some packets as the FIFO gets full.
I think its because of the internal design user_fifo that is between the transmit & recieve interface of the user application.
I am unable to get an understanding of the signal credit_control which is part of the module
It says that it is there to provide credit control and that it is for rate control of the User_fifo. But i am not able to remove this signal from the transmit state machine. If i do, the packets recieved in wireshark are all of incorrect size & data.
Q) Does this signal control the user_fifo so that it deosnt get filled??
Q) Why does the tx_axis_tready signal in pat_gen_inst always HIGH??
Q) I cannot transmit UDP packets with a gap of 1us b/w them using the 1Gbps mode but can do for the 10/100Mbps?
If anyone has any experience desiging with this core. please guide me.
My design files that i have edited are attached. Contains .v files of all the modules of example design.
I have edited the following module in the example design
08-28-2014 08:26 AM
Sameed, i sent you a message asking a question about example design on AC701. I would be very appreciated if you could spare a little time for it.
08-31-2014 11:41 PM
Will someone please followup on this issue??
I will be really grateful if someone with experience of TEMAC core designing provides some insight into this problem.