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Observer
Observer
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Registered: ‎07-27-2018

Ultrascale + 100G Ethernet IP : CAUI4 mode configuration

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I have simulated a simple data transfer and loopback design in Vivado which uses 100G ethernet IP . The simulation is running properly using the CAUI 10 mode ( 10 lanes*10G) but when I change the mode to CAUI 4 , the 100G IP Tx and Rx are not aligning and the data transfer does not begin.

For the CAUI10 mode , the alignment takes around 100-200 ms in vivado simulation which is similar to the 100G example design.

My question is whether I need to make any extra changes to the IP configuration when switching to CAUI4  or is there any specific changes needed in my design ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

The GT or shared logic will change when switching between CAUI-10 and CAUI-4.  If these wrappers are not included in the core they will need to be update in your design. 

You can diff the example design files for the CAUI-10 vs CAUI-4 designs.

If that is not it, I'd suggest comparing the core level input signals in simulation between your design and the working example design. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

When CAUI-4/CAUI-10 "Runtime Switchable" mode is selected in the GUI, the example design that is created will have wrapper files needed to switch the core and GT between the two modes/line rates.  Have you tried running the example design simulation for core generated with the runtime switchable mode?

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Observer
Observer
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Registered: ‎07-27-2018

.Actually I am not using the runtime switchable mode. I first simulated my design with the IP configured in  CAUI 10 mode which worked fine . Then when I change the IP configuration to CAUI 4 and run another simulation, the tx and rx don't align. 

 

For the example deisgn I have simulated both the CAUI 10 and CAUI 4 modes seperately and in both cases the simulation works fine.

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Xilinx Employee
Xilinx Employee
691 Views
Registered: ‎04-16-2008

The GT or shared logic will change when switching between CAUI-10 and CAUI-4.  If these wrappers are not included in the core they will need to be update in your design. 

You can diff the example design files for the CAUI-10 vs CAUI-4 designs.

If that is not it, I'd suggest comparing the core level input signals in simulation between your design and the working example design. 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post