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Registered: ‎07-27-2018

Ultrascale+ 100G ethernet IP : Loopback design working in simulation but failing on board

I am working on a loopback design of the 100G ethernet IP where I generate test data of AXI stream packets , then convert this data to LBUS protocol using custom AXIS to LBUS converter. This data is then fed to he Ultrascale+ 100G IP ( CAUI4 mode) and after GTY loopback is sent to custom LBUS to AXIS converter. Finally, I check the received data with the transmitted data. The design is working fine in Vivado simulation and i am able to receive the data properly.

After synthesis and implementation, when i generate the bitstream and port it to my board ( ZCU111) , I am not able to achieve Tx-Rx synchronisation ( rx_aligned signal is low) and hence data transfer is not initiated. 

Is this a problem with GTY or 100G CMAC itself ? I would like to know possible checks which can be introduced in the design to debug this problem as the simulation is showing no such errors.

Even if you have some experience with similar issues of porting a design to the board , please share how you solved the problem.

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2 Replies
Registered: ‎03-23-2019

I have the same issue, I am using Sidewinder Board xczu19eg, rx_gt_locked_led & rx_busy_led on, the rest off.
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Xilinx Employee
Xilinx Employee
Registered: ‎05-11-2012

Hi Guys,

I'd start with the Hardware Debug section of PG203 p264. This would be the general order of things to check:

The following sequence helps to isolate ethernet-specific problems:
1. Clean up Signal Integrity.
2. Ensure that each SerDes achieves CDR lock.
3. Check that each lane has achieved word alignment.
4. Check that lane alignment has been achieved.
5. Proceed to Interface Debug and Protocol Debug, of which there are a collection of diagnostic signals which you can check and read.