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Observer
Observer
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Registered: ‎07-27-2018

Ultrascale+ 100G ethernet IP

We want to establish data transfer between processor and 100G Ethernet MAC. 10G Ethernet MAC supports AXI which can also be used at Memory side. 100 G does not supports AXI for data transfer. Could you guide us on how can we transfer the data between DDR and 100G MAC using AXI or LBUS.

Thank You
Ashutosh
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Moderator
Moderator
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Registered: ‎04-01-2018

Hi @ashutoshs1799

 

I believe you are looking for AXI4-Stream option of 10G Ethernet MAC equivalence in 100G Ethernet MAC. In that case it is LBUS which can be a user interface. 

  • For AXI4 it uses Xilinx AXI Memory-Mapped Protocol Version 1.8
  • For LBUS is designed to match commonly used packet bus protocols made common by the SPI4.2 and Interlaken protocols.

As per as interface between LBUS and DDR it is not direct, needs user logic.

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Observer
Observer
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Registered: ‎07-27-2018

Thanks for your reply!!

 

As it is a new concept for me ,I would appreciate if you could provide some references for the LBUS interface and would like to have an idea of how to implement data transfer from memory in the processing system to the 100G ethernet CMAC IP present in the Programmable logic(PL)  part via the LBUS interface.

 

Thank you

Ashutosh

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