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Newbie kevincwork
Newbie
5,430 Views
Registered: ‎06-23-2016

Ultrascale Integrated Interlaken Example Design

Hi,

 

I'm currently trying to run an Integrated Interlaken (PG169) example design. On my custom board, we have 2 FMC connectors with a cable going across the two. There are 4 quads connected to each FMC. Basically, I want to do the example design with TX from one FMC and RX to the other FMC.

 

Now, the proper implementation is probably just have 2 example designs running one in "TX Simple" and  one in "RX Simplex" mode, however those modes are not supported. The only option left is the Duplex mode, which expects the TX to come back into the same quad RX (not possible with my SEARAY cable).

 

My question is that can I simply map the RX pins to another quad? (the one in our other FMC connector). If not, is there any way to run an example design on my board? 

 

Thanks,

Kevin

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Newbie kevincwork
Newbie
5,426 Views
Registered: ‎06-23-2016

Re: Ultrascale Integrated Interlaken Example Design

One idea I have is that I would generate two Interlaken cores (One in Simplex TX, ons in Simplex RX), and then use those to reaplce the interlaken_0.v of the example design. I'm not sure how difficult the stitching of the cores are going to be.

 

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Xilinx Employee
Xilinx Employee
4,204 Views
Registered: ‎02-06-2013

Re: Ultrascale Integrated Interlaken Example Design

Hi

 

The example design supports simple tx and simple RX modes

 

Refer from page 101 of below doc

http://www.xilinx.com/support/documentation/ip_documentation/interlaken/v1_8/pg169-interlaken.pdf

Regards,

Satish

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Newbie kevincwork
Newbie
3,785 Views
Registered: ‎06-23-2016

Re: Ultrascale Integrated Interlaken Example Design

On that exact page, it says "IMPORTANT: Simplex TX mode and Simplex RX mode are not supported in this release."

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Xilinx Employee
Xilinx Employee
3,698 Views
Registered: ‎02-06-2013

Re: Ultrascale Integrated Interlaken Example Design

Hi

 

Which version of core are you using?

 

Version 1.5 and  higher do support simplex modes and this can be found in the core generation GUI options 

Regards,

Satish

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Xilinx Employee
Xilinx Employee
3,583 Views
Registered: ‎02-06-2013

Re: Ultrascale Integrated Interlaken Example Design

Hi

 

I gave feed back on the warning in the PG and it will be removed in the PG as it is no longer valid in the latest revisions.

Regards,

Satish

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