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Visitor
Visitor
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Registered: ‎03-12-2013

Using external Marvell PHY with SGMII

I have a external Marvell 88Q2112 PHY I'm trying to connect using SGMII to a Zynq-7000 xc7z030sbg485-1.  In my block design I added a "1G/2.5G Ethernet PCS/PMA or SGMII IP".  It's configured with an SGMII standard, using a device specific transceiver.  I followed XAPP1082 as a reference in wiring up this IP.

I moved on to working at the PS code (baremetal).  The Marvell PHY uses clause 45 register access instead of clause 22.  I know this will take some modifications.  I'm able to talk with the Marvell PHY over MDIO.  I'm now looking at the SGMII part of the interface.  Here's where I'm a bit stuck/unsure.  In addition to my PHY there is a Xilinx IP responding on the MDIO lines.  It responds to the address I set on the "phyaddr[4:0]" port of the "1G/2.5G Ethernet PCS/PMA or SGMII IP".  Is this what the Marvell PHY link needs to auto-negotiate/link with?  Or is the Marvell PHY linking across the network cable?

Looking further in "xemacpsif_physpeed.c" I see the "phy_setup" function which loops through PHY addresses looking for devices.  Is this looking for my external PHY or the Xilinx IP?  Similarly it then calls "get_IEEE_phy_speed" which has some "XEmacPs_PhyRead" calls.  Is this talking to the Xilinx IP?  Is this:

XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);

  while ( !(status & IEEE_STAT_AUTONEGOTIATE_COMPLETE) ) 
  {
    sleep(1);
    XEmacPs_PhyRead(xemacpsp, phy_addr, IEEE_STATUS_REG_OFFSET, &status);
  }
waiting for autonegotiation between the Marvell PHY and the Xilinx IP?  I assume I just need to configure the external PHY then run these functions which will configure the Xilinx IP?
 
From reading the Marvell PHY registers it doesn't seem to be linking/auto-negotiating.  Any other ideas on what might be the issue?
 
Thanks
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3 Replies
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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @gunnerone ,

MAC is the MDIO master and any other PHYs - "1G/2.5G Ethernet PCS/PMA or SGMII IP" and external marvel PHY will be considered as MDIO slaves. These two "phys" need to have different PHY addresses and they are sharing the same MDIO. The phyaddr of PCS/PMA IP is the phy address for the core.

Please note that AN only happens at the PHY layer. In this case, it's PCS/PMA core and extenral marvel phy. After AN is done, the registers in PCS/PMA will updated and the SW will need to get auto-negotiated value before updating MAC.

In PG047, there is a section talking about problems with AN (page 240). Please take a look at this and see if that helps.

 

"Don't forget to reply, kudo and accept as solution."
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Visitor
Visitor
660 Views
Registered: ‎03-12-2013

Ok, I'm making some progress now.  The RX polarity was reversed.

So after I attempt auto-negotiation, register 1 from the PCS/PMA IP is 0x01EC, which should mean auto-negotiation is complete and the link is up:

BitsNameValueDescription
1.15100BASE-T40100BASE-T4 is not supported
1.14100BASE-X Full Duplex0100BASE-X full duplex is not supported
1.13100BASE-X Half Duplex0100BASE-X half duplex is not supported
1.1210 Mb/s Full Duplex010 Mb/s full duplex is not supported
1.1110 Mb/s Half Duplex010 Mb/s half duplex is not supported
1.10100BASE-T2 Full Duplex0100BASE-T2 full duplex is not supported
1.9100BASE-T2 Half Duplex0100BASE-T2 Half Duplex is not supported
1.8Extended Status1Extended register present
1.7Unidirectional Ability1 
1.6MF Preamble Suppression1Management Frame Preamble Suppression is supported
1.5Auto- Negotiation Complete1Auto-Negotiation process completed
1.4Remote Fault0No remote fault condition detected
1.3Auto-Negotiation Ability1PHY is capable of Auto-Negotiation
1.2Link Status1Link is up
1.1Jabber Detect0Jabber Detect is not supported
1.0Extended Capability0No extended register set is supported

 

The status vector is 0x1A0B which should mean: no pause, no remote fault, full duplex, 1000 Mb/s, PHY Link status not linked, Core is receiving Idles, Core is not receiving Auto-neg config sequences, Link synchronized, Link is valid

Is this saying that the MAC is successfully linked with my external PHY, but my external PHY isn't linked over the wire to another outside PHY?

When I read register 5 from the PCS/PMA IP I get 0x5801 which also says that the PHY Link status is down

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @gunnerone ,

Yes, that seems like the issue.

Have you tried to disable AN on both sides of the link to see if you can obtain a link?

 

"Don't forget to reply, kudo and accept as solution."