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Observer disa
Registered: ‎01-17-2014

VC709 - VC707 connectivity



we are designing a multi-board system using these two boards, and we need a connection between them using optical link. As a first test we instantiated two 10GEMAC + 10GBASE-R on VC709 and did a loopback over optical cable, which passed with flying colors. However, when we try to use two boards, we have certain problems. Our setup is as follows:


- VC709 generates 156.25 MHz clock which is forwarded to MGTREFCLK SMA connectors of both boards

- VC709 is the first board to be turned on / programmed (device A from Debug chapter in PG068). PCS/PMA indicates a local fault which is observed in ILA module

- VC707 is started after, and sends IDLE sequence (stage 2 of link bring-up); verified in ILA.


This status is kept infinitely and we believe that stage 3.1 "Device A PCS/PMA RX detects idles, synchronizes and aligns." is never finished. The VC709 stays in fault mode.


We tried setting Fault Inhibit bit if Reconciliation Sublayer to 1, which allowed us to transmit via VC709 and receive the sequence correctly on the other board. With this we concluded that both tx and rx on device B (VC707) are working properly, while only tx is operational on Device A (VC709).


Do you have a suggestion how to take it out of fault mode, or if there something else that we are missing? Thanks.


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1 Reply
Registered: ‎02-22-2010

Re: VC709 - VC707 connectivity

Hi Disa,


As per PG068, "This means that the latching Local Fault  and Link Status bits in the status vector or MDIO registers must be cleared with the associated Reset bits in the Configuration vector or by reading the MDIO registers, or by issuing a PMA or PCS reset".


Bottom line, you need to periodically reset the Local Fault and Link Status bits until they are cleared (zero).

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