In general, there are two basic design flows to use when targeting Versal ACAP, ie, Vitis Environment Design Flow and Vivado Tools Design Flow. Vivado IP Integrator is the primary flow for non-AI Engine-based projects, and is recommended to use for Ethernet designs creation targeting Versal.
Please refer to UG1273Chapter 4 – “Design Flow” for more detailed information.
For all PL Ethernet IPs, transceivers IPs (GTs) are separated completely. Use Block Automation within IP Integrator for Ethernet IP to GT integration. Please refer to PG331 Chapter 4 - “Xilinx IP - GT Quad Integration” for more details. All designs require the CIPS IP, which contains the PMC used to boot the device. For more information, see the Control Interface and Processing System IP Product Guide (PG352).
For PS GEMs, they are sitting inside CIPS. Please refer to PG352 for CIPS product guide.
IP Product Guides and Master ARs
Here is a list of the Ethernet IPs with their product guides and release notes and known issues master ARs: