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Adventurer
Adventurer
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Registered: ‎01-24-2018

Which reg should be used to monitor error on TX/RX of CMAC 100G

 

Hi, 

When using 100G CMAC ( CAUI-4, RS-FEC enabled, GT is included in IP, ) in Kintex Ultra Plus FPGA,

SW wants to monitor the error related to TX and RX of CMAC. 

Which set of registers we should use to monitor?  Because there are so many error registers in CMAC IP according to PG203.

0x0218 STAT_RX_AM_ERR_REG

0x021C STAT_RX_AM_LEN_ERR_REG

0x0220 STAT_RX_AM_REPEAT_ERR_REG

0x02C0 STAT_RX_BIP_ERR_0 

- - - - - 

0x0358 STAT_RX_BIP_ERR_19

0x0360 STAT_RX_FRAMING_ERR_0

- - - - - 

0x03F8 STAT_RX_FRAMING_ERR_19

0x0458 STAT_TX_FRAME_ERROR

0x101C STAT_RX_RSFEC_ERR_COUNT0_INC

0x1024 STAT_RX_RSFEC_ERR_COUNT1_INC

0x102C STAT_RX_RSFEC_ERR_COUNT2_INC

0x1034 STAT_RX_RSFEC_ERR_COUNT3_INC

 

 

 

 

Thank you so much in advance!

Best,

 

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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

Because I did below features implementation in CMAC IP,

I think some registers in CMAC are not activated in my design. Is this understanding correct?

For example, because I did not enable AN/LT logic,

so the register (from 0x0258 to 0x0278) as shown below should not available. Is this understanding correct?

0x0258 STAT_AN_STATUS_REG
0x025C STAT_AN_ABILITY_REG
0x0260 STAT_AN_LINK_CTL_REG

0x0264 STAT_LT_STATUS_REG1
0x0268 STAT_LT_STATUS_REG2
0x026C STAT_LT_STATUS_REG3
0x0270 STAT_LT_STATUS_REG4
0x0274 STAT_LT_COEFFICIENT0_REG
0x0278 STAT_LT_COEFFICIENT1_REG

 

 

cmac_reg_access1.png
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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

In above reply, we can see the CMAC configuration in my current design.

Another question is since some features are not implemented in my design, for example AN/LT

if I read the registers related to AN/LT, what will happen?

 

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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

The test log about accessing CMAC reg is shown below

Looks like if user accesses the register related to the disabled feature, CMAC returns the value belonging to the register in previous read operation.

Is this result correct??? 

server1:~$ ./i104diag -r 0x120224
SUCCESS: Read data from reg[0x00120224] = 0x000FFFFF, </dev/xdma0_user>
server1:~$
server1:~$
server1:~$ ./i104diag -r 0x120238
SUCCESS: Read data from reg[0x00120238] = 0x000000CD, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x12023c                                         <--- it is register related to TX OTN, which is not enabled in my design
SUCCESS: Read data from reg[0x0012023C] = 0x000000CD, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120224
SUCCESS: Read data from reg[0x00120224] = 0x000FFFFF, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120228
SUCCESS: Read data from reg[0x00120228] = 0x0A418820, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x12022c
SUCCESS: Read data from reg[0x0012022C] = 0x16A4A0E6, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120224
SUCCESS: Read data from reg[0x00120224] = 0x000FFFFF, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120238
SUCCESS: Read data from reg[0x00120238] = 0x000000FF, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x12023c                             <--- it is register related to TX OTN, which is not enabled in my design
SUCCESS: Read data from reg[0x0012023C] = 0x000000FF, </dev/xdma0_user>
server1:~$
server1:~$
server1:~$ ./i104diag -r 0x120238
SUCCESS: Read data from reg[0x00120238] = 0x000000BD, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120234
SUCCESS: Read data from reg[0x00120234] = 0x00000272, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120214
SUCCESS: Read data from reg[0x00120214] = 0x00000000, </dev/xdma0_user>
server1:~$ ./i104diag -r 0x120210
SUCCESS: Read data from reg[0x00120210] = 0x000FFFFF, </dev/xdma0_user>
server1:~$
server1:~$ ./i104diag -r 0x12023c                         <--- it is register related to TX OTN, which is not enabled in my design
SUCCESS: Read data from reg[0x0012023C] = 0x000FFFFF, </dev/xdma0_user>
server1:~$
server1:~$

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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

In my design, CMAC reg's offset addr is  0x120000. and I am trying to access below registers.

 

Untitled.png
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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

If the feature is not enabled for the core, then the associated registers are not included to keep size down.

The 100G Ethernet come has a number of error counters. 

On TX you can use stat_tx_frame_err to count number of frame aborted by asserting tx_errin input.

On RX at MAC level you can see number of frame marked bad due to FCS error with stat_rx_bad_fcs/stat_rx_packet_bad_fcs.

On RX at PHY level you can check for error blocks with stat_rx_bad_code and stat_rx_bip_err will indicate if there is error in alignment marker bip check. 

Further information on each statistics signal can be found in the stat_* port description.  When statistics counters are not included the stat_* ports are provided to give increments to an external counter.

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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

Hi Ejanney,

 

Thank you for your reply.

So which feature I should enable for the core in order to include the error register related to TX and RX?

Because I did enable RS-FEC in my core, so I think all of the error registers related to RS-FEC should be included in the core. Is it correct?

 

 

 

Thank you very much!

Best,

 

Best,

Zan

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-16-2008

Yes, if FEC is enabled you should also have the FEC error stats as well.  The other error statistic counters I mentioned earlier are always enabled for all of the CMAC core options with the AXI lite interface and statistics counters.

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Adventurer
Adventurer
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Registered: ‎01-24-2018

 

Hi Ejanney,

 

I try to read out registers 0x458, 0x500, 0x508, 0x510 and 0x518, however read out all 0 from these register. 

Do you happen to know why the read-out values are all 0?

Is it because I disabled the OTN of CMAC Core?

 

Best,

Zan

cmac_tx_reg.png
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