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Adventurer
Adventurer
2,508 Views
Registered: ‎11-11-2015

Why JESD rx_tvalid goes low intermittently?

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Hi everyone,

 

I'm using a Virtex 7 FPGA board (HTG700) to interface an ADC evaluation board (ADC12J4000). The project has been built and the FPGA can receive the ADC sampled data correctly. 

 

However, the rx_tvalid pin of the JESD receiver in FPGA keeps going low  intermittently, and I cannot find out the reason.

 

jesd_rx_tvalid.png

 

I checked the JESD IP product guide (PG066) but cannot find a solution, also the the methods (AR# 58747, AR# 55503) in Xilinx solution center didn't work.

 

Is there any possible solution for this problem?

 

Thank you very much.

 

Regards,

Tong

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Adventurer
Adventurer
3,345 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

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hi @hpoetzl,

 

I solved this problem. I got a document ( http://www.ti.com/lit/pdf/slau580) from TI and configured the ADC12J4000 as described in section 6.3.

 

I also modified the FPGA design to set the JESD reference clock = lane rate / 20, and core clock = lane rate / 40. 

After the modification, the rx_tvalid interruption problem is gone.

 

Thank you very much.

 

Regards,

Tong

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Voyager
Voyager
2,492 Views
Registered: ‎06-24-2013

Re: Why JESD rx_tvalid goes low intermittently?

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Hey @onlinext,

 

However, the rx_tvalid pin of the JESD receiver in FPGA keeps going low intermittently ...

.. and I cannot find out the reason.

In the JESD receiver core, the rx_tvalid signals that the rx_tdata is valid in this clock cycle.

 

Unless your communication produces exactly the amount of data which is required to keep the AXI interface busy all the time, it is expected that not all cycles will contain valid data and thus rx_tvalid will go low.

 

Note that rx_tvalid is no indication whatsoever of the quality of the connection, except maybe if it never goes high because then you can assume that no data is received.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
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Adventurer
Adventurer
2,438 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

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Hi @hpoetzl,

 

Thank you for your reply. I knew that it is expected that the rx_tvalid will go low if the AXI interface is not busy all the time.

 

However, in my case the AXI interface should be busy all the time, since the ADC is sampling the waveform and sending the data through JESD continuously. The ADC acts as the JESD transmitter and the FPGA acts as the JESD receiver. So it is supposed that the rx_tvalid should be high all the time, otherwise some data will be lost.

 

Could you tell me if there is any way to find out why the rx_tvalid is going low? Is this caused by some mistake in my FPGA design or the drawback of ADC board?

 

Regards,

Tong 

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Voyager
Voyager
2,430 Views
Registered: ‎06-24-2013

Re: Why JESD rx_tvalid goes low intermittently?

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Hey @onlinext,

 

Thank you for your reply.

You're welcome!

 

in my case the AXI interface should be busy all the time ...

That is a very interesting setup, care to share the sampling rate as well as the serial clock frequency?

 

it is supposed that the rx_tvalid should be high all the time, otherwise some data will be lost.

Did you check Sync Status, Link Error and the Error Counters in the JESD204 Register Space?

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Adventurer
Adventurer
2,426 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

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Hi @hpoetzl,

 

Thank you very much.

 

The sampling frequency of our DAC is 2.7GHz, the line rate is 5.4Gbps. Both the reference clock and core clock are 135MHz. 

 

I haven't checked the "Sync Status, Link Error and the Error Counters" you mentioned. I'm still not familiar with the mechanism of JESD. But I have a Microblaze in my design, shall I use it to read the JESD registers space continuously?

 

Regards,

Tong

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Voyager
Voyager
2,422 Views
Registered: ‎06-24-2013

Re: Why JESD rx_tvalid goes low intermittently?

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Hey @onlinext,

 

The sampling frequency of our DAC is 2.7GHz, the line rate is 5.4Gbps

So we are talking JESD204B here, very likely with several lanes?

 

I have a Microblaze in my design, shall I use it to read the JESD registers space continuously?

It's probably sufficient to check the registers via some debug probe just to see if there are problems.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Adventurer
Adventurer
2,414 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

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hi @hpoetzl,

 

Yes we are talking about JESD. In this configuration, the number of JESD lane is 8, and the link parameters are as follows.

jesd_link_parameters.png

I'll check the register space and give you feedback.

 

Thank you very much.

 

Regards,

Tong

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Adventurer
Adventurer
2,402 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

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hi @hpoetzl,

 

I read the value of these parameters from JESD register space.

I read many sets of these values, and here are one set of values (in hex).

 

Link Error Status: 00BC0058
Error Reporting: 0
Sync Status 00010001
Link Error count: 0

 

I don't know how to enable the link error counters, I tried the writing register function in Microblaze but it doesn't work. So the value of "Link Error Count" is invalid.

 

link_error_status.png

From the value of "Link Error Status" we can see that link error occurred during the operation of JESD core. Could you tell me what I should do to fix this problem?

 

Thank you very much.

 

Regards,

Tong

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Highlighted
Adventurer
Adventurer
3,346 Views
Registered: ‎11-11-2015

Re: Why JESD rx_tvalid goes low intermittently?

Jump to solution

hi @hpoetzl,

 

I solved this problem. I got a document ( http://www.ti.com/lit/pdf/slau580) from TI and configured the ADC12J4000 as described in section 6.3.

 

I also modified the FPGA design to set the JESD reference clock = lane rate / 20, and core clock = lane rate / 40. 

After the modification, the rx_tvalid interruption problem is gone.

 

Thank you very much.

 

Regards,

Tong

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Voyager
Voyager
2,370 Views
Registered: ‎06-24-2013

Re: Why JESD rx_tvalid goes low intermittently?

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Hey @onlinext,

 

So you matched the sampling rate to the JESD data rate, which naturally makes every frame count and thus rx_tvalid doesn't go low.

 

Glad it could be 'resolved'.

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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