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bitjockey
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Registered: ‎03-21-2011

Why no SelectIO 1000BASE-X on 7 Series 1G Ethernet Logicore?

Why does the 1.0/2.5G Ethernet LogiCore https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_2/pg047-gig-eth-pcs-pma.pdf only support 1G SGMII mode for the SelectIO implementation on the 7-series chips and not 1000base-X also?  Is it impossible or just not implemented [yet]?

Is there something fundamentally different about the bitrate/encoding? I thought they were both 1.25Gbps LVDS 8B10B encoded symbols.  Only some of the control codes were interpreted differently.  So if 1G SGMII is possible in the IP on the 7-series (using this neat oversampling trick it appears! wow! cool!) why not 1000base-X?

Is there a fundamental, intrinsic, electrical limit of the chip?  Or just an extrinsic IP limitation?  Are there any other IP cores that just do the PCS layer that could interface to the xapp523 PMA implementation for 1000base-X?  Before I look at the scope of writing one from scratch myself.   Or perhaps a way to generate the xilinx cores in two different modes and try and merge them?

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nanz
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Registered: ‎08-25-2009

Hi @bitjockey ,

The Sync SGMII over LVDS will use one pair of input differential clock (normally to a IBUFDS) to a single clock module, and the rest of the clocks are generated from it.

For Async, this input clock can be async to the incoming data within the limits as per spec. The reference clock also comes into a IBUFDS but goes into two PLLs which can drive the BITSLICE_CONTROL.

625MHz is the clock that we support/validated for Async option. Other frequencies may fail timing on US devices. 

So we did not add the support for 7 series and the customer can try themselves by referring to XAPP523. That said, this interface cannot directly support 1000BASE-X. Users can refer to US implementation but this is not supported by the IP and out of our support scope. 

Hope this helps. 


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bitjockey
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Registered: ‎03-21-2011

Sorry @nanz I'm not quite understanding.  I guess I should have specified Async in both cases.  I'm referring to both Async columns in Table 2-1.  Where it says 1000Base-X : Async LVDS SelectIO = no, but SGMII : Async LVDS SelectIO = yes (via xapp 523...).   Both SGMII and 1000Base-X run off a 625MHz DDR clock with the same bandwidth, signal levels, same 8B10B encoding, etc. no?

So this isn't an inherent limit of the chip (different bandwidths/frequencies jitter) just a design/support choice?  By "not natively support" you just mean there's no check-boxes in the IP generation and no plans for Xilinx to add them?  Not that the silicon/fabric can't do it due to a physical limit?

 If one were to attempt it themselves do you have any suggestions? Would it be possible for a customer to generate an SGMII ref, strip it for the oversampling front-end and the Data Recovery Unit from the xapp, with all its internal state machines, then tie it to a ripped-out base-X back-end from a different implementation?

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nanz
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Registered: ‎08-25-2009

Hi @bitjockey ,

That's correct there are no known chip limitations. We only have XAPP523 as an example.  


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