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Observer pmm
Observer
923 Views
Registered: ‎07-11-2017

ZCU102 - 10G/25G Example Design

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Hello everyone,

Has anyone managed to succesfully run the 10G Ethernet Subsystem example design on the ZCU102 board ? When I run the test I get stuck in "completion_status = TX timed out" (using the GPIO LEDs to debug).

More details about my setup:

  • ZCU102
  • 10G/25G High Speed Ethernet Subsystem v2.5
  • Vivado 2018.3
  • 10GBASE-R SFP + SMF in loopback

Core configuration:

  • 10G Ethernet MAC + PCS/PMA 64-bit - BASE-R
  • Control and Status Vectors
  • GT subcore in core
  • GT RefClk = 156.25 MHz (using the onboard Programmable User MGT Clock default freq)
  • GT DRP Clock = 125.00 MHz (using the onboard CLK_125_P/N and routing it to a IBUFDS primitive to obtain "dclk")
  • GT Selection = Quad X1Y3 / Lane X1Y12  (Right Top SFP)
  • Include Shared Logic in example design

Results:

  • Both GT and RX block lock are asserted and I've verified that the reference clocks have the correct frequency.
  • If send_continous_pkts_0 = 1'b1 (Sends continuous packets for board) I get "completion_status = TX timed out".
  • If send_continous_pkts_0 = 1'b0 (Sends fixed 20 packets for simulation) I got "completion_status  = PASSED 25GE/10GE CORE TEST SUCCESSFULLY
    COMPLETED."

But what does "Sends fixed 20 packets for simulation" even mean ? I'm running this directly on hardware...

I also tested the PCS and PMA internal loopbacks and the results are the same. What leads me to think that the problem is whithin the example design.

 

Thanks for any help you can provide,

Best regards,

Pedro Marques.

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1 Solution

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Moderator
Moderator
861 Views
Registered: ‎04-01-2018

Re: ZCU102 - 10G/25G Example Design

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Hi @pmm 

I beleive the results of running example design on ZCU102 in your post are in sync with example design.

For  send_continous_pkts_0 = 1'b1 (Sends continuous packets for board) I get "completion_status = TX timed out".

I beleive you have already aware of FSM in xxv_ethernet_0_pkt_gen_mon.v file  which decides Completion status.

Consider the tx_packet_count for the setting of continuous_pkts:

forumpost.png

tx_packet_count decides internal counters and FSM gives timeout when it is selected for send_continuous_pkts as high. 

 

 

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4 Replies
Moderator
Moderator
862 Views
Registered: ‎04-01-2018

Re: ZCU102 - 10G/25G Example Design

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Hi @pmm 

I beleive the results of running example design on ZCU102 in your post are in sync with example design.

For  send_continous_pkts_0 = 1'b1 (Sends continuous packets for board) I get "completion_status = TX timed out".

I beleive you have already aware of FSM in xxv_ethernet_0_pkt_gen_mon.v file  which decides Completion status.

Consider the tx_packet_count for the setting of continuous_pkts:

forumpost.png

tx_packet_count decides internal counters and FSM gives timeout when it is selected for send_continuous_pkts as high. 

 

 

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Observer pmm
Observer
844 Views
Registered: ‎07-11-2017

Re: ZCU102 - 10G/25G Example Design

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Thanks @kgadde for the reply,

I think I understand what you mean.

So since I'm getting "completion_status  = PASSED 25GE/10GE CORE TEST SUCCESSFULLY COMPLETED" when using send_continous_pkts_0 = 1'b0 (only sends 20 packets) I'm going to assume that everything is fine with the example design and start to develop my own logic on top of it. I also deployed some ILA debug cores and everything seems fine.

BR

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Contributor
Contributor
688 Views
Registered: ‎10-29-2018

Re: ZCU102 - 10G/25G Example Design

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Dear Sir,

I had been working on 10G/25G Example design. I successfully experimented the design on ZCU102 evaluation board. In example design , packet generator and monitor is generating 20 packets and monitoring it. Now I want to develop my own logic on top of this logic design. I want to send data packet from 3 bit counter to 10G/25G ethernet subsystem and receive it back. Also I want to compare received data with transmitted data.

I do not have any idea how to do the same. Can you please guide me?

Thank you and Regards,

Puja Kumari

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Observer pmm
Observer
628 Views
Registered: ‎07-11-2017

Re: ZCU102 - 10G/25G Example Design

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Hi Puja,

I would say that the next step would be to develop your own packet generator logic to format your data (3-bit counter) into packets that need to be provided to the MAC core. Check the PG210 - 10G/25G High Speed
Ethernet Subsystem for more info on the interfaces. You can use the packet generator and monitor modules from the example design as a base and modify them to suit your needs.

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