03-28-2019 03:59 PM
We designed a board using a XC7Z030-2 to support SGMII from a Marvell 88E1512. We're trying to use standard LVDS inputs on an HR bank with VCCO = 2.5V. Currently we're trying to use internal LVDS differential termination, so it's a direct connect between the Zynq-7000 and the 88E1512. We can get RGMII ethernet to work, but not SGMII. (The Ethernet PHY is pinned out so we can use SGMII or RGMII.)
Do I need to add AC coupling and DC biasing similar to what's shown in UG471, Figure 1-72, page 93?
I thought that I might have come across something specifying this for SGMII with the Zynq-7000 family, but I can't find anything on it now.
04-15-2019 11:53 PM
Electrical interface of Marvell 88E1512 is CML and FPGA electrical interface is LVDS.
Check the parameters like CML output driver, VODIFF, VICM_DC and VOL & VOH.
Yes you may need to connect AC coupling and DC biasing.
04-16-2019 10:50 AM
Thank you for the reply. I added external AC coupling and DC termination to the SGMII differential pairs since I couldn't find anything in the documenation. In the past on other FPGA's I've been able to direct connect these lines, but maybe that doesn't work on this device. We have RGMII working, so weren't overly concerned, but would like to track down the issue. Our board should be back in a few weeks and we can test it out.