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Registered: ‎04-04-2019

Zync Ultrascale+ ZU2CG: PL-Ethernet solutions (SGMII)

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Dear Xilinx-Members,

I chose the ZU2CG-derivate from the Ultrascale+-series for a new design. The ZU2CG has no SerDes-transceivers (GT) in the PL.

I checked the Ethernet solution AppNotes "xapp1305-ps-pl-based-ethernet-solution.pdf" and "pg047-gig-eth-pcs-pma.pdf".

As I understood, I have two possibilities to implement the SGMII-interface in the PL:

1) Using PS GEM through EMIO: This solutions requires GT's in the PL => The ZU2CG don't have them.

Thus, it is not possible with the ZU2CG.

2) Asynchronous SGMII over LVDS: This solution does support the embedded clock in the data stream. It don't require any GTs in the PL.

Thus, it can be implemented on the ZU2CG.

 

First question: Is my understanding correct?

Additionally, it is possible to use one of the GEMs in the PS to use SGMII (with embedded clock) and route internally the TX-data from the PL to the PS respectively the RX-data from the PS to the PL.

Next questions:

- If this is possible, is there any CPU-interaction required to transfer the SGMII-data from PS<=>PL or are these just DMA-transfers?

- What is the maximum latency for this transaction (PS<=>PL)?

 

Thanks in advance!

Julian

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Registered: ‎08-25-2009

Re: Zync Ultrascale+ ZU2CG: PL-Ethernet solutions (SGMII)

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Hi @dj_hbk ,

Yes, your understnading is correct. PS EMIO SGMII requires GTs on PL. And SGMII over LVDS might be a solutuon for you.

To consider using PS GEM SGMII using PS-GTR, can you please be more specific on your data flow? This is not supposed to go through PL but external SGMII PHY directly.

 

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Registered: ‎08-25-2009

Re: Zync Ultrascale+ ZU2CG: PL-Ethernet solutions (SGMII)

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Hi @dj_hbk ,

Yes, your understnading is correct. PS EMIO SGMII requires GTs on PL. And SGMII over LVDS might be a solutuon for you.

To consider using PS GEM SGMII using PS-GTR, can you please be more specific on your data flow? This is not supposed to go through PL but external SGMII PHY directly.

 

"Don't forget to reply, kudo and accept as solution."

View solution in original post

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Registered: ‎04-04-2019

Re: Zync Ultrascale+ ZU2CG: PL-Ethernet solutions (SGMII)

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Thank you nanz!

I want to connect two FPGAs with SGMII. One is the PL of the ZU2CG and the other one with SerDes-Transceivers.

The data I get from the second FPGA must be processed in the PL before this data goes to the PS.

So my question is, if I use the PS to connect the second FPGA via SGMII, how much latency and CPU-utilization will add up, when I first have to send this data to the PL of the ZU2CG?

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Re: Zync Ultrascale+ ZU2CG: PL-Ethernet solutions (SGMII)

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Hello again,

can also confirm that we can use the GEMs from the PS-domain and share the data with the PL via FIFO:

https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

=> Page 933

-GEM DMA engine as a master on the PS AXI interconnect (LPD) with a 32-bit data access width

-Slave interface in the PL via the external FIFO interface with an 8-bit data access width

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