01-08-2021 01:56 AM
For a next project on Zynq7000 (030 or 045) , we need to integrate two (2) 10G Ethernet link. We wondering if it is possible on those components or not ?
I've saw that IP 10 Gigabit Ethernet Subsystem is available on Zynq7000, but specifies that a -2 speed grade at least is required. The datasheet of this IP, PG157, gives the ressources used by the IP, but only for Kintex and Artix.
Can you provide me more information about those IP ? And especially if this type of ethernet interface can be used on a Zynq7 device and/or if there is limitations
01-08-2021 04:20 AM
@mhed You are correct that the 10 Gigabit Ethernet Subsystem Product Guide (PG157; v3.1) states that Zynq-7000 SoC is supported in a minimum of -2 speed grade. Zynq-7000 has a consistent Processing System (PS) throughout the family but the Programmable Logic (PL) utilizes the Artix-7 for the Cost-Optimized Devices and utilizes the Kintex-7 for the Mid-Range Devices in the family (see below).
The XC7Z030 or XC7Z045 devices are part of the Mid-Range Devices and contain the Kintex-7 Programmable Logic. Therefore, you would reference the Kintex-7 portion of PG157.
You can create a Vivado Managed IP project to target the 10G Ethernet Subsystem LogiCORE IP and configure it to your desired implementation. You can then right-click the generated IP and select to "Open IP Example Design..." and verify you can implement for your specific target.
I selected the XC7Z045-2FFG900 for the example design and it successfully implemented. I did not generate the bitstream as there are several I/Os that need to be constrained (PACKAGE_PIN and IOSTANDARD) but note the transceivers were successfully placed and routed.
01-12-2021 01:58 AM
Ok thank you for your answer.
So, if i understand correctly, it is possible to implement this IP on a Zynq 045 (with a speed grade -2). It is confirmed by your example.
But is it possible to have 2 instance of this IP? For example is a limitation on frequency or on bandwidth ?
01-13-2021 01:59 AM
Hi @mhed ,
Yes, it's possible as long as the FPGA resources allow on the board.
01-13-2021 02:15 AM
You can try to deploy those without even the board. If it generates the bitstream, good. About bandwidth it's not so straightforward. Usually hardware (IP and DMA) can keep the data rate, bandwidth limitations usually come from sw multitasking things and not being able to kick data on time.
01-27-2021 04:06 AM
Hi @mhed ,
If your question has been answered, could you please mark the relevant thread as "accepted solution"? So it will benefit also other forum users. Thank you!