Zynq 7000 Support for 10GbE

[joe306]

Hello, I'm in the middle of Zynq 7000 Z030 design and now told to consider adding 10 Gigabit Ethernet and not sure if the Z030 will support it. I am using MGTX transceivers that support 12.5Gb/s. I see in the IP Catalog a 10G Ethernet MAC IP but I am not sure what other IP I need or even if this the right IP to use. Are there any reference schematics that have implemented 10GbE?

Thank you,

Joe

[nanz]

Hi @joe306 ,

10G is supported on Zynq. If you are looking at implementing a processor based design then you should look at AXI10G Ethernet Subsystem IP.

But unfortunately, we do not have a reference design based on it.

[joe306]

Hello, thank you for responding to my message. I started looking a the 10 Gigabit Ethernet Subsytem v3.1 PG157. I will also look at the AXI10G Ethernet Subsystem IP. Quick question, I will need to connect to a Fiber-optic Transceiver will the AXI10G Ethernet have a RX Pair and TX Pair to interface with the Fiber-optic transceiver?

Respectfully,
Joe

[joe306]

Hello, I don't see the AXI10G Ethernet Subsystem you mentioned.

Which IP in the image above should I try?

Thank you,

Joe

[nanz · Accepted solution]

Hi @joe306 ,

Sorry, that is the 10G Ethernet Subsystem IP I mean. 

[joe306]

Great! That's the documentation I'm looking at. Thank you, Joe

[joe306]

Hello, one more question, what is 10G Ethernet PCS/PMA (10GBASE-R/KR)?

Thank you

[nanz]

Hi @joe306 ,

The PCS/PMA is implementing the physical layer functions which does not include MAC.

The -KR has the AN/LT and -R does not. 

[joe306]

Hello, thank you for responding to my message. Seems like I would want PCS/PMA+MAC, does that sound reasonable?

Joe

[nanz]

HI @joe306 ,

Yes, mostly likely you will be using -R or -KR PHY/SFP+ so you will need the PCS/PMA.

[joe306]

Hello, I'm a little confused, I thought I did not need a PHY I thought I could go directly to a SFP connector. Am I incorrect?

[joe306]

I should mention that I am no longer using the Zynq-7000 but a Zynq Ultrascale+ MPSOC part#XCZU7CG-1FFVC1517I.

[joe306]

If you are saying that I need a PHY I found this on the web:

You mentioned KR so I'm thinking I need a PHY that has a KR interface. Am I correct?

Thank you

[joe306]

I have a ZCU106 Board and I quickly dropped in a 10G/25G Ethernet Substation and then clicked on Run Automation and it wired up the gt_serial port to sfp_1x. So I'm thinking that I can connect the SFP fiber transceiver directly up to the FPGA MGT pins that are connected to the IP.
Am I correct?

[barriet]

The short story is the combination of PCS/PMA (GTH) and the external SFP+ 10G Base-R optical module are effectively your PHY here.

Check out XAPP1305 - it was originally a traditional pdf application note but now can be found here:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/478937213/MPSoC+PS+and+PL+Ethernet+Example+Projects
https://github.com/Xilinx-Wiki-Projects/ZCU102-Ethernet

There's quite a few forum threads too on the subject if you search for XAPP1305 and 10G or 10GE.

But you can see how it (10GE using the PL & GTH) was done with the ZU+ ZCU102 board and an SFP module for 10GE using an SFP module.

[joe306]

Wonderful! My schematics are all done and finding a external PHY would put me behind schedule. Thank you very much for your quick reply. I will look at the ZCU102 board and maybe there is a reference design that shows how things are connected to the PS-side.
Thank you very much,
Joe

[barriet]

To clarify, I think most of the connections here are on the PL (e.g. GTH) side... Admittedly SFP has some signals like I2C so there's a bit of flexibility here - I guess you could do that from the PS MIO - but check to see how they connected it here (it has been awhile since I looked at it in detail)... But there's a bit of confusion here possibly because XAPP1305 includes:

-10GE in the PL (10/25G Ethernet Subsystem).

-1GE in the PL AXI Ethernet Subsystem

-1GE in the PS GEM

And the ZCU102 is a bit more complicated than perhaps necessary - it uses a Si570 which is programmable for the GT ref clock so you'll find some setup there for the right clock (156.25MHz vs 125MHz) rate - i'd expect a chip-down design would just have the right clock rate supported by the 10G PCS/PMA... And the ZCU102 has a SI5328B for clock recovery for synchronous protocols like CPRI - I wouldn't expect you'd need that for 10GE... So XAPP1305 is a good starting point but has a bit of complexity that can make you scratch your head because of some of this.

Also note that this is 10GE only fixed rate - not other rates like 1GE.

Cheers,

bt

[joe306]

Hello, thank you for the information. I am doing my schematics right now but quickly added the IP to a ZCU106 Example Design.

[joe306]

I just wanted to get the IP in the Block design and connect it up to the PS IP to see how things look.

Any comments please?