11-04-2020 08:34 AM
Hello, I'm in the middle of Zynq 7000 Z030 design and now told to consider adding 10 Gigabit Ethernet and not sure if the Z030 will support it. I am using MGTX transceivers that support 12.5Gb/s. I see in the IP Catalog a 10G Ethernet MAC IP but I am not sure what other IP I need or even if this the right IP to use. Are there any reference schematics that have implemented 10GbE?
11-05-2020 06:30 AM
Hi @joe306 ,
10G is supported on Zynq. If you are looking at implementing a processor based design then you should look at AXI10G Ethernet Subsystem IP.
But unfortunately, we do not have a reference design based on it.
11-05-2020 07:03 AM
12-02-2020 01:41 AM
12-02-2020 01:35 PM
12-02-2020 02:15 PM
If you are saying that I need a PHY I found this on the web:
You mentioned KR so I'm thinking I need a PHY that has a KR interface. Am I correct?
12-02-2020 02:46 PM
12-02-2020 03:51 PM
The short story is the combination of PCS/PMA (GTH) and the external SFP+ 10G Base-R optical module are effectively your PHY here.
Check out XAPP1305 - it was originally a traditional pdf application note but now can be found here:
There's quite a few forum threads too on the subject if you search for XAPP1305 and 10G or 10GE.
But you can see how it (10GE using the PL & GTH) was done with the ZU+ ZCU102 board and an SFP module for 10GE using an SFP module.
12-02-2020 03:56 PM
12-02-2020 04:07 PM
To clarify, I think most of the connections here are on the PL (e.g. GTH) side... Admittedly SFP has some signals like I2C so there's a bit of flexibility here - I guess you could do that from the PS MIO - but check to see how they connected it here (it has been awhile since I looked at it in detail)... But there's a bit of confusion here possibly because XAPP1305 includes:
-10GE in the PL (10/25G Ethernet Subsystem).
-1GE in the PL AXI Ethernet Subsystem
-1GE in the PS GEM
And the ZCU102 is a bit more complicated than perhaps necessary - it uses a Si570 which is programmable for the GT ref clock so you'll find some setup there for the right clock (156.25MHz vs 125MHz) rate - i'd expect a chip-down design would just have the right clock rate supported by the 10G PCS/PMA... And the ZCU102 has a SI5328B for clock recovery for synchronous protocols like CPRI - I wouldn't expect you'd need that for 10GE... So XAPP1305 is a good starting point but has a bit of complexity that can make you scratch your head because of some of this.
Also note that this is 10GE only fixed rate - not other rates like 1GE.