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Registered: ‎10-04-2019

Zynq ultrascale+ PL only 1G ethernet

Hi everyone,

I am trying to develop a 1G ethernet solution that uses only the PL part of the Zynq ultrascale+ (no ARM core), the board I am using is ZCU102. 

The data flow should looks like this: data coming from ADC ==> DSP ==> ethernet ==> Host PC pos-processing 

This link looks simple but I don't find any example or similar project online. 

I also read about the xilinx xapp1305 ps-pl based ethernet reference designs, there are PL based design however it seems they all have the PS part involved.  

Is PL only ethernet possible at all on zcu102? If yes, can anyone help me with some good suggestion?

Thanks a lot people!

 

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Registered: ‎08-25-2009

Re: Zynq ultrascale+ PL only 1G ethernet

Hi hongru.han@gmail.com ,

We do not have an example as you requested. In XAPP1305 PL ethernet design, it uses 1G/2.5G AXI Ethernet subsystem core which is mostly used in a processor based application as it has the AXI Ethernet buffer from which the processor can access to the registers. 

In your application, do you need AXI Ethernet subsystem core or only a TEMAC IP is enough? I'd suggest reading PG138 and PG051/PG046 for more details about the IPs first.

 

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