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Observer
Observer
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Registered: ‎12-19-2019

autonegotiation not working in simulation for GMII to SGMII bridge

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Hi,

 

We are using Xilinx GMII to SGMII bridge to interface to a custom GMII MAC inside FPGA and an SGMII PHY chip outside FPGA. We plan to operate at gigabit rate.

While trying to simulate the bridge in Questasim, we are seeing that soon after reset deassertion, Xilinx bridge starts transmitting autonegotiation ordered sets but with config reg value of all 0s. At the input of 8b10b encoder, input is seen as follows -

(/K28.5/D10.5/config[15:0],   /K28.5/D2.2./config[15:0].  

We tried setting config [15:0] = 0x01a0  (FD = 1, PS1 = 1, PS2 =1) and toggled AN restart bit from 1 -> 0 -> 1. However that did not have any effect and config data continues to be 0.

What is the way to get this AN config data to be used by the Xilinx IP ?

Regards

Sandeep Sathe

 

 

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

It slipped my mind to inform you that after doing MDIO programming, my DUT is transmitting and receiving data packets to/from testbench VIP.

I indeed aprreciate your quick responses to each of my query.

Thanks a lot indeed, and once again very much appreciate your help.

Regards

Sandeep J. Sathe

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Do you use SGMII IP core (PG047)?

Do you enable MDIO?

Have you selected PHY mode?

AN simulation takes long time? How long time have you run? You can change link timer value to shorten AN time.

Do you see GT TX/RXRESETDONE asserted? What're the GT RXDATA?

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

Thanks for your reply. Our connectivity is as follows -

Custom MAC with GMII interface followed by Xilinx GMII to SGMII Bridge  -- inside V7 FPGA

TI SGMII PHY on VC707 board + RJ45 -- outside V7 FPGA, on VC707 board.

However in simulation, we are directly hooking up Mentor's SGMII VIP to Xilinx SGMII bridge. So there is no actual PHY in the simulation environment.

About Resets -- We are seeing some problem with Reset synchronizer output going 'U' in gig_ethernet_pcs_pma_0_Clock_Reset.vhd module. We are looking into this.

About RxData -- We are not getting comma alignment from the AN data transmitted by the Mentor VIP. We are discussing this with Mentor as well.

About Data transmitted by Xilinx IP - We see that soon after reset deassertion, Xilinx IP is transmitting below data for a short duration -

/K28.5/D10.5/16'b0/

/K28.5/D2.2/16'b0/

I suppose these are Auto-negotiation Ordered Sets, with config_reg == 16'h0 -- Is this right ?

We tried setting AN restart input to 1 and setting config_reg = 16'h01a0 (FD = 1, PS1 = 1, PS2 = 1), but we see that data pattern remains same. Can you comment on why new AN vector is not being taken ? As per design doc, 0 to 1 transition on AN restart input should trigger new AN sequence with new value.

Also, can you comment on why IP stops sending AN ordered sets after a very small duration (less than 1 microsecond I suppose. I can give you exact duration if required)

Regards

Sandeep

 

 

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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1. Keep an_adv_config_vector=01a0 and assert/deassert an_adv_config_val twice

Let me know if it can change the AN values

2. Are data always BCB5 0000 BC42 0000? Could you run 5ms and share the screenshot? Have data ever changed?

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Screenshot.png


@guozhenp wrote:

1. Keep an_adv_config_vector=01a0 and assert/deassert an_adv_config_val twice

Let me know if it can change the AN values

2. Are data always BCB5 0000 BC42 0000? Could you run 5ms and share the screenshot? Have data ever changed?


 

Screenshot.png
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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi,

 

I have uploaded screen shot of the waveform. I am not sure whether you can zoom into this waveform, but if not features that I sewe in this waveform are as follows -

1. 8b10b encoder input data is always BCB5_0000, BC42_0000 throughout the simulation

2. Differential output signals TXP and TXN toggle for very short duration, as you can see in the waveform. Actual duration is about 277 ns.

3. Verification person just now mentioned that gt_rxreset signal in pcs_pma_block module is pulsing periodically (pulse every 1us)

Regards

Sandeep

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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1. Please try GT PMA near end loopback or just connect GT TXP/TXN to RXP/RXN to run the loopback and check the result.

2. Could you try the IP core example design first? Does the example simulation work?

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

I wish you happy new year 2020.

I simulated GMII-SGMII Bridge example design inside Vivado. There also I do not see correct behavior. What I observed is as follows -

1. Differential output signals TXP/TXN are not toggling at all

2. RXP/RXN are toggling but signal decoded_rxchariscomma is 'x' throughout the simulation. al_rx_valid_out, al_rx_data_out[9:0] are also x. (I suppose this is 10-bit boundary aligned Rx data)

3. Also, in this example design simulation, I do not see any RTL hierarchy below the trasceiver module. But in the actual design, I see 8b10b encoder, decoder, 1 bit to 10 alignment module (serdes_1_to_10) etc under transceiver.  Will that have any impact ?

4. I am wondering shall I zip the Vivado output folder, or the simulation folder and upload here so that you can simulate the same design ?

Regards

Sandeep

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Please just right click on the IP core .xci in Vivado and generate the example design.

Do you mean even the example design simulation fails? How long time have you run in simulation?

 

What's the Vivado version? What's the FPGA device details?

You can provide the screenshots or the details on the settings when you generate the IP and select them in GUI.

Then we can also generate the IP core to check its example design.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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What's the simulator?

Can you have a try on Vivado Simulator first? Does it work?

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi,

I am simulating inside vivado only. That is what I am calling as Xilinx isim.
I was going through a similar thread posted a year or so ago. In that thread it was suggested to try generating AXI Ethernet core, because example design of that IP also demonstrates how SGMII operates over LVDS. May be we can try that also.

Any other suggestion ?

Regards
Sandeep
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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

Sorry for the delayed response. I got diverted to some other activity and resuming this Ethernet debug now.

Actually, we were also having some problem with VHDL compilation, and that was causing some reset misbehavior. We have fixed that, and after that there is slight improvement on Rx side but Tx side is still behaving the same.

On Rx side, we see that 8b10b decoder is getting enabled periodically and gearbox output is the pattern 0xbc 0xb5 0x21 0x00 which looks like AN pattern transmitted from the Mentor SGMII VIP in the testbench.

However on Tx side, we still see repeated data pattern 0xbc 0xb5 0x00 0x00,  0xbc 0x42 0x00 0x00. We also toggled an_restart input twice and drove an_config_vector [15:0] = 0x01A0, but this new AN value is not seen at the input of 8b10b encoder.

We are targetting this IP to FPGA VCU118,  and IP is generated using Vivado 2017.4. I do not have GUI snap shot, but the xci file is attached to this reply.

One more Q. Is it possible to disable Auto Negotiation process and make the core to transmit data received over GMII and send the received data over Rx GMII ?  We tried setting configuration_vector bit [4] to 0, and set configuration_valid to 1, but in this case we see data pattern of 0xbc 0x50 repeating, and we still do not see data sent over GMII being passed to 8b10b enocoder.

Any suggestions on how to proceed further ?

Thanks and regards

Sandeep

 

 

 

 

 

 

 

 

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2013

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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How long time have you run? AN takes long time in simulation.

Please use the following command in Vivado to speed up the simulation

set_property CONFIG.EXAMPLE_SIMULATION {1} [get_ips gig_ethernet_pcs_pma_0]

And then run 200us, check the result.

 

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

I ran Vivado simulation with the set_property command that you suggested. In Vivado waveforms, I do see Tx GMII data reaching 8b10b encoder input. Some more Questions -

1. In Vivado waveforms I see an_config_vector [15:0] = 0x0021, and an_restart is always 0. Has autonegotiation happened in this test case or not ? I see AN complete interrupt to be 0. So I think AN has not occured. Is that true ?

2. I see some MDIO pulsing in Vivado waveforms. Is MDIO activity really required ? I see MDIO tri-state control as high. I suppose this means data is being written from testbench to the DUT. Are these writes really required ?

 

 

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Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

Further, in our Questasim simulation waveforms, I still see Tx input of 8b10b encoder to be 0xbcb5 0xbc42. I do not see data from Tx GMII.

Also, on Rx Side, in one of the simulations we tried setting configuration_valid input to 1. In this case we observed that the data sent from the Mentor VIP in the testbench was being driven to the Rx GMII inputs of our MAC. However when configuration_valid was changed back to 0, there is no data being drivne to the Rx GMII bus even if I see that data at the 8b10b decoder output. What are the correct settings for data reception to be correct ?

Regards

Sandeep

 

 

 

 

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Observer
Observer
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Registered: ‎12-19-2019

回复: autonegotiation not working in simulation for GMII to SGMII bridge

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Hi Guozhenp,

It slipped my mind to inform you that after doing MDIO programming, my DUT is transmitting and receiving data packets to/from testbench VIP.

I indeed aprreciate your quick responses to each of my query.

Thanks a lot indeed, and once again very much appreciate your help.

Regards

Sandeep J. Sathe

 

 

 

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