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designer1918
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Registered: ‎07-25-2014

charisk problem of Virtex5-85T GTP Transciver

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Dear Xilinx Engineer:

 

I have used  "0" diff pair of 4 tile transmiters to transmit "tx_data_in" and receive them by the same tile receivers'

"0" diff pair, tile0_txusrclk20_i can driver the 4 tiles successfully and the line rate is 3.125Gbps.

The Verilog code is as following:

 

parameter idle = 16'h95BC;

always @(posedge tile0_txusrclk20_i)

begin

         if(!reset)begin

                   tile0_txdata0_i <= 0;

                   tile1_txdata0_i <= 0;

                   tile2_txdata0_i <= 0;

                   tile3_txdata0_i <= 0;

                   tile0_txcharisk0_i <= 2'b00;

                   tile1_txcharisk0_i <= 2'b00;

                   tile2_txcharisk0_i <= 2'b00;

                   tile3_txcharisk0_i <= 2'b00;

         end

         else if(!tx_fifo_valid)begin

                   tile0_txdata0_i <= idle;

                   tile1_txdata0_i <= idle;

                   tile2_txdata0_i <= idle;

                   tile3_txdata0_i <= idle;

                   tile0_txcharisk0_i <= 2'b01;

                   tile1_txcharisk0_i <= 2'b01;

                   tile2_txcharisk0_i <= 2'b01;

                   tile3_txcharisk0_i <= 2'b01;

         end

         else begin

                   tile0_txdata0_i <= tx_data_in;

                   tile1_txdata0_i <= tx_data_in;

                   tile2_txdata0_i <= tx_data_in;

                   tile3_txdata0_i <= tx_data_in;

                   tile0_txcharisk0_i <= 2'b00;

                   tile1_txcharisk0_i <= 2'b00;

                   tile2_txcharisk0_i <= 2'b00;

                   tile3_txcharisk0_i <= 2'b00;   

         end

end

 

There are two problems when I used the ChipScope to capture the  tileX_rx_data0_i and tileX_rxcharisk as Pic_1 and

Pic_2 showing:

 

1. When the TX idle code is 16'h95BC, the RX idle code BC95 and 95BC are presented randomly in  tile0_rx_data0_i, 

tile1_rx_data0_i,  tile2_rx_data0_i,  tile3_rx_data0_i by burning program every time. When the RX idle code is 95BC,

the upper byte and low byte of  the following tileX_rx_data0_i is coincided with the tx_data_in, but when the RX idle

code is BC95, the upper byte and low byte of the following tileX_rx_data0_i are reversed to the tx_data_in, so I need

to use the tileX_rxcharisk to recover the byte order of the tileX_rx_data0_i.

 

2. when the RX idle is 95BC, the related tileX_rxcharisk is righrt, but when the RX idle code is BC95, the related

tileX_rxcharisk is always "0", so that I can not use the  tileX_rxcharisk to sepetare the RX idle code and the RX

 

Additionally (not showing in the pictures), if I change the TX idle code to 16'hBC95 (with tileX_txcharisk0_i <=

2'b10), the RX idle code BC95 and 95BC are presented randomly in  tile0_rx_data0_i,  tile1_rx_data0_i, 

tile2_rx_data0_i,  tile3_rx_data0_i by burning program every time.  When the RX idle code is 95BC,  the upper byte and

low byte of the following tileX_rx_data0_i are reversed to the tx_data_in, and the related tileX_rxcharisk is righrt. 

When the RX idle code is BC95, the upper byte and low byte of  the following tileX_rx_data0_i is coincided with the

tx_data_in, and the related tileX_rxcharisk is always "0".

 

These problem are really borthering me, very thanks for your help!

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venkata
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15,422 Views
Registered: ‎02-16-2010
Check if AR#25385 shows some relevance to your observations
http://www.xilinx.com/support/answers/25385.html
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designer1918
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Registered: ‎07-25-2014

Pic_1Pic_1.jpg

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designer1918
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Visitor
8,808 Views
Registered: ‎07-25-2014

Pic_2Pic_2.jpg

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venkata
Moderator
Moderator
15,423 Views
Registered: ‎02-16-2010
Check if AR#25385 shows some relevance to your observations
http://www.xilinx.com/support/answers/25385.html
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

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