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narsee
Visitor
Visitor
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Registered: ‎04-27-2021

configuring axi 1g/2.5g Ethernet Subsystem for kintex ultrascale kcu105 in SGMII over LVDS mode for 1Gbps , full duplex jumbo frame support

Hi all, 

I am trying to  configure axi 1G/2.5G Ethernet Subsystem for kintex ultrascale board for 1Gbps speed on kintex ultrascale kcu 105 board. 

following are the configurations 

BOARD INTERFACES:

ethernet : sgmii lvds

MDIO : mdio mdc

DIFFCLK :SGMII PHYCLK

PHYRST_N : PHY_RESET OUT

PHYSICAL INTERFACES

ethernet speed : 1gbps

physical interface selection : SGMII

LVDS option : enable standard I/O

MAC features

disable processor 

enable statistics counters , 64 bit width 

frame filter Enable 

Network timing  : default

Shared logic and OOC settings : default 

 

I opened the example design (see image attached ), while opening wrapper block in MaC IP,  PHY Interface is Internal and below it given that The example design will not implement a Physical Interface .

I generated bit stream for the example desigh and programmed the Board but I could see any interface taking place

so

1. to implement Physical interface with this example design what do i have to do ?

2 can we change that Phy Interface (internal ) to GMII/RGMII and what does internal PHY interface exaclty does. 

3. which Phy interface connects to RJ45 ethernet connector and to stablish the data transfer through RJ 45 exaclty what modifications to do.

4. in example design certain mtrlb_config data are given (as shown in attached pic ) what they are and what they are doing exaclty.

5. to slablish the link between PC and board what all address(SA, DA , PHY address , ip_dest_addr,ip_src_addr, tcp_dest_port,tcp_src_port,udp_dest_port,udp_src_port)  are required and where can i find them ?

and finally to make this example design working on kcu105  board what all things i have to do ,

 

please help !!

thanks    

 

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7 Replies
nanz
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557 Views
Registered: ‎08-25-2009

Hi @narsee ,

Are you aware of this example:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841604/KCU105+SGMII+over+LVDS+design+creation+using+board+flow

You can still follow the steps if not using the exact same version of the tools. 


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narsee
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Registered: ‎04-27-2021

hi @nanz 

I have tried that but there are some issues as I'm using vivado 2020.2 version and in that I am not able to launch SDK , vitis is there but i am not able to launch as it shows failed to launch , secondly I don't know what all constrains are required there .

 

please help me  with that also 

thanks 

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nanz
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Registered: ‎08-25-2009

Hi @narsee ,

If you are using the complete board flow, the constraints should be set for you correctly when you add board interface to your designs. If there are some custom parts that need to be constrained, you will need to manually set them. 

If using 2020.2, there will be no SDK. SDK is replaced by Vitis, but it's the same thing. 

If Vitis failed to launch, do you have any messages? Did you install Vitis correctly? Can you start it from scratch rather than from Vivado? 


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nanz
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Registered: ‎08-25-2009

Hi @narsee ,

Have you made any progress on the issue please?


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nanz
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Registered: ‎08-25-2009

Hi @narsee,

If you have an update regarding the issue, could you please update the thread so that other forum users will also benefit from it? Thank you!


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narsee
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Registered: ‎04-27-2021

Hi @nanz

I have successfully implemented MAC on Kintex Ultrascale KCU105 board. My Requirements was to establish Gigabit Ethernet Interface with jumbo frame support in KCU105 board for that following are the configurations-

1. Since this board have SGMII so AXI Ethernet Subsystem IPcore was used.

 following are the configurations

BOARD INTERFACES:

ethernet : sgmii lvds

MDIO : mdio mdc

DIFFCLK :SGMII PHYCLK

PHYRST_N : PHY_RESET OUT

PHYSICAL INTERFACES

ethernet speed : 1gbps physical

interface selection : SGMII LVDS

option : enable standard I/O

MAC features :

disable processor enable statistics counters ,

64 bit width frame filter Enable

Network timing : default

Shared logic and OOC settings : default

configure the IP as given above and then right clock on IP and Right click -> open example design

in contraints file connect the MDIO, MDC pin to board pins (look into UG for the pin Numbers)

generate bit stream and enjoy

 

nanz
Moderator
Moderator
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Registered: ‎08-25-2009

Hi @narsee ,

Great to hear you've got this working. Could you please mark your thread as accepted solution? So it will benefit other forum users. Thank you!


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Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs and our Versal Ethernet Sticky Note.

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