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superdetka
Adventurer
Adventurer
4,207 Views
Registered: ‎11-17-2010

how to use created ip core(serial rapidIO v5.5) in my design?

Hello!

I created serial rapidIO v5.5 core in Xilinx ISE 12.3 with a help of CoreGenerator.  In  the hierarchy <my_core's_name>.xco appeared. In project directory i see folder  "ipcore_dir", in this folder  *.vho, *.vhd files exists(rio_buffer.vho, srio_phy_v5_5.vho, rio_log_io_v5_5.vho), but i cant see them in hierarchy tree in ISE.  If i try to attach them to this tree ISE tells me that this files already exist in project. If i open them, for example "rio_log_io_v5_5.vho" , and add that code in my parent design , my parent design cant see the vhdl component(component rio_log_io_v5_5). So how can i attach core to my parent desing? Maybe somebody give me some links where i can find good answer on this question.

Thank you.

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luisb
Xilinx Employee
Xilinx Employee
4,194 Views
Registered: ‎04-06-2010

For the SRIO core, I would start off by taking a look at the getting started guide.

http://www.xilinx.com/support/documentation/ip_documentation/srio_gsg247.pdf

 

The getting started guide will show you how to use the example design that comes with the logical and physical layer cores.  The example design also includes other files that many uses use in their final designs.  The common files include the rio_buffer and the reset module.

 

There's also a tcl script in the output files that will generate an ISE project for you that includes the SRIO example design.  The script is called create_ise_prj.tcl  This will show you how an SRIO project may appear within the ISE GUI.  It's not same as a simple FIFO Generator core.  

 

-hope this helps.

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Anonymous
Not applicable
3,756 Views

Hello. Generated example is in verilog. How to generate example in VHDL?

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Anonymous
Not applicable
3,750 Views

In coregen in the top bar click on Project and then Project Options. Select Generation. Here you can change Design Entry to be VHDL instead of Verilog.

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