11-17-2010 12:03 PM
I created serial rapidIO v5.5 core in Xilinx ISE 12.3 with a help of CoreGenerator. In the hierarchy <my_core's_name>.xco appeared. In project directory i see folder "ipcore_dir", in this folder *.vho, *.vhd files exists(rio_buffer.vho, srio_phy_v5_5.vho, rio_log_io_v5_5.vho), but i cant see them in hierarchy tree in ISE. If i try to attach them to this tree ISE tells me that this files already exist in project. If i open them, for example "rio_log_io_v5_5.vho" , and add that code in my parent design , my parent design cant see the vhdl component(component rio_log_io_v5_5). So how can i attach core to my parent desing? Maybe somebody give me some links where i can find good answer on this question.
11-17-2010 07:24 PM
For the SRIO core, I would start off by taking a look at the getting started guide.
The getting started guide will show you how to use the example design that comes with the logical and physical layer cores. The example design also includes other files that many uses use in their final designs. The common files include the rio_buffer and the reset module.
There's also a tcl script in the output files that will generate an ISE project for you that includes the SRIO example design. The script is called create_ise_prj.tcl This will show you how an SRIO project may appear within the ISE GUI. It's not same as a simple FIFO Generator core.
-hope this helps.