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amit_kumar
Observer
Observer
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Registered: ‎06-19-2019

ila vio chipscope in aurora 8b10b.

I implemented the loopback single lane (full duplex) on the board (kintax ultrascale development board). In there, ILA, VIO core are there to probe out the signals in the chipscope. For single lane, I have defined (RXP, RXN, TXP, and TXN) physical pin on my fpga. So, I thought of connecting the TXP and TXN to RXP and RXN respectively, So, that it will make a loop and I will be able to transmit and receive the data. But, even before connecting the wire. setting loopback VIO to high is showing the RX and TX data. How is that happening? 

Capture1.PNG

Please help.

thanks.

 

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rkhatri
Moderator
Moderator
395 Views
Registered: ‎01-10-2019

Hi @amit_kumar ,

Are you using vivado generated example design ?
Can you please try to run the simulation design without connecting TX to RX and check if you still receive the data .

Thanks,
Rahul Khatri
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