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Visitor santosh321
Visitor
5,558 Views
Registered: ‎07-30-2008

implementing back to back 1G PCS

i am new to Xilinx products and desgin environment. I want to try to implement 1G PCS back to back. There is already a IP core for the same. Can anybody tell me how to go about it.

 

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Xilinx Employee
Xilinx Employee
5,535 Views
Registered: ‎08-02-2007

Re: implementing back to back 1G PCS

If you mean the interface to the TBI, here is the IP core.

http://www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm

 

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Visitor santosh321
Visitor
5,529 Views
Registered: ‎07-30-2008

Re: implementing back to back 1G PCS

thanks for that link but i am sure somebody who is asking a question would have seen tht page multiple times. Anyway thanks for the reply. I will once agin reiterate the problem:-

 

Using 1G "PCS/PMA or SGMII" IP core included with xilinx ISE, i have to to take 2 instances of this. Then pass data to one and loop the data back through the other PCS. Although the data can be looped back through the same instance using recieve side, but i want to implement it on seperate instances.

 

Can anyone help me out in this by giving logical steps as to what i should do.

 

i also tried to simulate example provided with core, but it results in the error while compiling in modelsim XE starter version. it shows multiple errors mainly like "cant change directory etc." and then ends up in error in both timing and functional simulations.

 

Thanks for the help

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