11-05-2017 08:26 PM
hi
I am available with ml505 virtex5 fpga. i am trying to implement example design of aurora 8b/10b core with single lane . i am selecting GTPY3 TILE 0 which is having loopback and onboard 125 mhz clock. i routed lane up and channel up signal to leds. but it is not blinked. how i implemnt this example design. will you reply the steps?
is tre any board setting changes?
thank you
12-21-2017 12:19 AM
Hi
please check the following
pin LOC constraints related to Refclk and init_clk
check the INIT_CLK source on board and frequency of INIT_CLK.
Are you doing the external loopback.?
please let me know what is the Tool Version you are using