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200982
Adventurer
Adventurer
2,637 Views
Registered: ‎10-27-2011

pop twice from FSL in two clocks

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Hello,

 

I am a little bit unsettled.

As far as I can see in the FSL documentation, it is possible to pop twice from FSL in two clocks.Unbenannt.jpg

But when I try to do so, I still get the old data at the second read action.

entity user_logic is
  port(
  FSL_Clk      : in  std_logic;
  FSL_Rst      : in  std_logic;
  FSL_S_Read   : out std_logic;
  FSL_S_Data   : in std_logic_vector(0 to 31);
  FSL_S_Exists : in  std_logic; );
end entity user_logic;

architecture EX of user_logic is

  signal fsl_s_data_i : std_logic_vector(31 downto 0);

begin  
     
  fsl_s_data_i    <= FSL_S_Data;

  PROCCOLI : process ( FSL_Clk) is 
  begin
    if ( FSL_Clk'event and FSL_Clk = '1') then
      case state is

          when one =>
            if FSL_S_Exists = '1' then
              var <= fsl_s_data_i;
              FSL_S_Read <= '1';
              state      <= two;
            else
              FSL_S_Read <= '0';
            end if;
    
          when two =>
            if FSL_S_Exists = '1' then
              var <= fsl_s_data_i;
-- this is still the old value. Why?
              FSL_S_Read <= '1';
              state      <= done;
            else
              FSL_S_Read <= '0';
            end if;
     
         end case;
    end if;
  end process;
end architicture;

 So what's wrong? Is it me or is it the documentation?

Do I really have to pause one clk after popping from FSL? 

 

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200982
Adventurer
Adventurer
2,836 Views
Registered: ‎10-27-2011

SOLVED

 

didnt know its got to be combinatorial. 

View solution in original post

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200982
Adventurer
Adventurer
2,837 Views
Registered: ‎10-27-2011

SOLVED

 

didnt know its got to be combinatorial. 

View solution in original post

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