UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
932 Views
Registered: ‎05-11-2018

problem SGMII IP VC707 receiver path

Jump to solution

Hello,

 

I'm trying to use the SGMII IP for the VC707 fpga board to establish a connection between my PC and my FPGA board.

I instantiated the SGMII IP and opened the example design i wrapped the example design in a TOP module.

I constrained the design with the following xdc file ( i modified the xcd file generated by the example design)

#***********************************************************
# The following constraints target the Transceiver Physical*
# Interface which is instantiated in the Example Design.   *
#***********************************************************
#-----------------------------------------------------------
# Transceiver I/O placement:                               -
#-----------------------------------------------------------
# Place the transceiver components, chosen for this example design
# *** These values should be modified according to your specific design ***

set_property LOC GTXE2_CHANNEL_X1Y27 [get_cells */*/*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i]

(Maybe this line is not suited fo the VC707?? ) #*********************************************************** # The following constraints target the GMII implemented in * # the Example Design. * #*********************************************************** # The GMII is intended to be an internal interface. * # The GMII signals should be connected directly to user * # logic and all of the following constraints in this file * # should be removed. * #*********************************************************** set_property PACKAGE_PIN AH7 [get_ports SYS_CLK_N] set_property PACKAGE_PIN AH8 [get_ports SYS_CLK_P] set_property IOSTANDARD LVDS [get_ports independent_clock_bufg_n] set_property PACKAGE_PIN E18 [get_ports independent_clock_bufg_n] set_property PACKAGE_PIN E19 [get_ports independent_clock_bufg_p] set_property IOSTANDARD LVDS [get_ports independent_clock_bufg_p] set_property PACKAGE_PIN AP40 [get_ports RESET] set_property IOSTANDARD LVCMOS18 [get_ports RESET] set_property PACKAGE_PIN AV39 [get_ports PHY_RESET_N] set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_N] set_property PACKAGE_PIN AR40 [get_ports RESET1] set_property IOSTANDARD LVCMOS18 [get_ports RESET1] set_property PACKAGE_PIN AM39 [get_ports LED] set_property IOSTANDARD LVCMOS18 [get_ports LED] set_property PACKAGE_PIN AM7 [get_ports RXN] set_property PACKAGE_PIN AM8 [get_ports RXP] set_property PACKAGE_PIN AN1 [get_ports TXN] set_property PACKAGE_PIN AN2 [get_ports TXP] set_property PACKAGE_PIN AJ33 [get_ports PHY_RESET] set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET]

I connected the ethernet cable to the PC and to the FPGA board, and then i type a ping command in the cmd window of my PC and i expect to see a rising edge on the signal gmii_rx_dv but nothing happens on the ILA debug core that i added

The trigger on the rising edge of gmii_rx_dv never happens

I don't know what to do, i verified that the design met the timing requirements

Does anyone have any idea?

Here is my TOP level vhd file



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity Top is
    Port (
        -- Clocks
        SYS_CLK_P             : in std_logic;     -- 125 Mhz
        SYS_CLK_N             : in std_logic;     -- 125 Mhz
        
        independent_clock_bufg_p : in std_logic;
        independent_clock_bufg_n : in std_logic;
        
        
        RESET                 : in std_logic;     -- Reset
        
        RESET1                : in std_logic;
        
        PHY_RESET_N             : in std_logic;
        
        LED                   : out std_logic;
        
        PHY_RESET             : out std_logic;
        
        TXP                   : out std_logic;     
        TXN                   : out std_logic;     
        
        RXP                   : in std_logic;     
        RXN                   : in std_logic      
    );
end entity Top;

architecture IMPL of Top is

component debounce IS
  GENERIC(
    counter_size  :  INTEGER := 20); --counter size (19 bits gives 10.5ms with 50MHz clock)
  PORT(
    clk     : IN  STD_LOGIC;  --input clock
    button  : IN  STD_LOGIC;  --input signal to be debounced
    result  : OUT STD_LOGIC); --debounced signal
END component debounce;

component gig_ethernet_pcs_pma_0_example_design is
      port(

      --An independent clock source used as the reference clock for an
      --IDELAYCTRL (if present) and for the main GT transceiver reset logic.
      --This example design assumes that this is of frequency 200MHz.
      independent_clock    : in std_logic;

      -- Tranceiver Interface
      -----------------------
      gtrefclk_p           : in std_logic;                     -- Differential +ve of reference clock for tranceiver: , very high quality
      gtrefclk_n           : in std_logic;                     -- Differential -ve of reference clock for tranceiver: , very high quality
      rxuserclk2           : out std_logic;                     -- Differential -ve of reference clock for tranceiver:, very high quality
      txp                  : out std_logic;                    -- Differential +ve of serial transmission from PMA to PMD.
      txn                  : out std_logic;                    -- Differential -ve of serial transmission from PMA to PMD.
      rxp                  : in std_logic;                     -- Differential +ve for serial reception from PMD to PMA.
      rxn                  : in std_logic;                     -- Differential -ve for serial reception from PMD to PMA.

      -- GMII Interface (client MAC <=> PCS)
      --------------------------------------
      sgmii_clk            : out std_logic;                    -- Clock for client MAC
      sgmii_rx_clk         : out std_logic;                    -- Clock for client MAC
      gmii_txd             : in std_logic_vector(7 downto 0);  -- Transmit data from client MAC.
      gmii_tx_en           : in std_logic;                     -- Transmit control signal from client MAC.
      gmii_tx_er           : in std_logic;                     -- Transmit control signal from client MAC.
      gmii_rxd             : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
      gmii_rx_dv           : out std_logic;                    -- Received control signal to client MAC.
      gmii_rx_er           : out std_logic;                    -- Received control signal to client MAC.
      -- Management: Alternative to MDIO Interface
      --------------------------------------------

      configuration_vector : in std_logic_vector(4 downto 0);  -- Alternative to MDIO interface.

      -- Speed Control
      ----------------
      speed_is_10_100      : in std_logic;                     -- Core should operate at either 10Mbps or 100Mbps speeds
      speed_is_100         : in std_logic;                     -- Core should operate at 100Mbps speed

      -- General IO's
      ---------------
      status_vector        : out std_logic_vector(15 downto 0); -- Core status.
      reset                : in std_logic;                     -- Asynchronous reset for entire core.
      signal_detect        : in std_logic                      -- Input from PMD to indicate presence of optical input.
      );
end component gig_ethernet_pcs_pma_0_example_design;

    -- signals
    
    -- Connect the following signals to 1G/2.5G Ethernet PCS/PMA or SGMII
    -- PHY_Speed is connected to status_vector(11 downto 10)
    signal tb_PHY_Speed        : std_logic_vector(1 downto 0); -- "11" Reserved, "10" 1000 Mb/s, "01" 100 Mb/s, "00" 10 Mb/s
    signal GMII_RXDV        : std_logic;
    signal GMII_RXD         : std_logic_vector(7 downto 0);
    signal GMII_RXERR       : std_logic;
    signal GMII_TXEN        : std_logic;
    signal GMII_TXD         : std_logic_vector(7 downto 0);
 
    signal tb_gmii_txd      : std_logic_vector(7 downto 0);
    signal tb_gmii_tx_en    : std_logic;
    signal tb_gmii_tx_er    : std_logic;
    signal tb_gmii_rxd      : std_logic_vector(7 downto 0);
    signal tb_gmii_rx_dv    : std_logic;
    signal tb_gmii_rx_er    : std_logic;
 
    signal tb_speed_is_10_100   : std_logic;
    signal tb_speed_is_100      : std_logic;

    signal tb_clk           : std_logic;
    signal tb_reset           : std_logic;
    signal tb_independent_clock_bufg           : std_logic;
    
    signal tb_mac_clock           : std_logic;
    
    signal tb_rxuserclk2             : std_logic;


    signal tb_rx_config              : std_logic_vector(79 downto 0);
    signal tb_tx_config              : std_logic_vector(79 downto 0);
    
    signal tb_s_rx_axis_fifo_tvalid  : std_logic;
    
    signal detect_edge : std_logic_vector( 1 downto 0);
    signal tb_s_arp_pkt_count : std_logic_vector(7 downto 0);
    
    signal tb_start : std_logic;
begin


   IBUFDS_inst : IBUFDS
   generic map (
      DIFF_TERM => FALSE, -- Differential Termination 
      IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT")
   port map (
      O => tb_independent_clock_bufg,  -- Buffer output
      I => independent_clock_bufg_p,  -- Diff_p buffer input (connect directly to top-level port)
      IB => independent_clock_bufg_n -- Diff_n buffer input (connect directly to top-level port)
   );

    gig_ethernet_pcs_pma_0_example_design_INST :  gig_ethernet_pcs_pma_0_example_design
      port Map(
      
      independent_clock               => tb_independent_clock_bufg,
      -- Transceiver Interface
      ---------------------

      gtrefclk_p                      => SYS_CLK_P,               
      gtrefclk_n                      => SYS_CLK_N,               
      
      txp                             => txp,                       
      txn                             => txn,                       
      rxp                             => rxp,                       
      rxn                             => rxn,                       
       
      rxuserclk2                  => open, --tb_mac_clock,         


      -- GMII Interface               -- GMII Interface         
      -----------------               -----------------         
      sgmii_clk                       => open,
      sgmii_rx_clk                    => open,

--      gmii_txd                        => gmii_txd,                  
--      gmii_tx_en                      => gmii_txen,                
--      gmii_tx_er                      => '0',                
--      gmii_rxd                        => gmii_rxd,                  
--      gmii_rx_dv                      => gmii_rxdv,                
--      gmii_rx_er                      => gmii_rxerr,                
       
      gmii_txd                        => tb_gmii_txd    ,           
      gmii_tx_en                      => tb_gmii_tx_en  ,   
      gmii_tx_er                      => tb_gmii_tx_er  ,     
      gmii_rxd                        => tb_gmii_rxd    ,      
      gmii_rx_dv                      => tb_gmii_rx_dv  ,     
      gmii_rx_er                      => tb_gmii_rx_er  ,
      
      -- Management: Alternati        -- Management: Alternati  
      ------------------------        ------------------------  

      configuration_vector            => "00000",      

      -- Speed Control                -- Speed Control          
      ----------------                ----------------          
      speed_is_10_100                 => '0',           
      speed_is_100                    => '0',              


      -- General IO's                 -- General IO's           
      ---------------                 ---------------           
      status_vector                   => open,             
      reset                           => tb_RESET,                     
     
      signal_detect                   => '1'            
 

      );


    
    debounce_INST : debounce
    PORT MAP(
        clk             => tb_independent_clock_bufg,      
        button          => RESET,   
        result          => tb_reset   
     );
    PHY_RESET <= not (PHY_RESET_N);

   
end architecture;

It's been a couple of weeks allready that i have this problem and don't know how to solve it

 

0 Kudos
1 Solution

Accepted Solutions
Adventurer
Adventurer
789 Views
Registered: ‎05-11-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

I finally found the solution, i had to enable the option auto negotiation in the SGMII IP and now it works fine

0 Kudos
7 Replies
Adventurer
Adventurer
925 Views
Registered: ‎05-11-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

I checked the status_vector on the ILA :

status_vector (15: 0) = 0000 0000 0000 0111

0 Kudos
Explorer
Explorer
899 Views
Registered: ‎07-17-2014

Re: problem SGMII IP VC707 receiver path

Jump to solution

@cassandra

No MDIO and MDC signals here? if not, it is impossible to move normally.

0 Kudos
Adventurer
Adventurer
879 Views
Registered: ‎05-11-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

Are you talking about the following pins?

AK33: PHY_MDIO

AL31 : PHY_INT

AL33: PHY_MDC

 

I didn't connect to them to any port because i configured the SGMII IP without the MDIO configuration option.

Do i have to tie these pins to '0'?

 

0 Kudos
Explorer
Explorer
862 Views
Registered: ‎07-17-2014

Re: problem SGMII IP VC707 receiver path

Jump to solution

@cassandra

yes ,it's these pins.
 
I haven't used this approach, so I don't know if you need to set it up.
but in my experience, it's not easy to use this IP, especially the first time.
Adventurer
Adventurer
842 Views
Registered: ‎05-11-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

Does anyone know to what value should i ties these pins to, knowing that i didn't use the MDIO configuration option in the SGMII IP that i instantiated?

0 Kudos
Adventurer
Adventurer
790 Views
Registered: ‎05-11-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

I finally found the solution, i had to enable the option auto negotiation in the SGMII IP and now it works fine

0 Kudos
Visitor 1315chw
Visitor
534 Views
Registered: ‎12-26-2018

Re: problem SGMII IP VC707 receiver path

Jump to solution

Hello,cassandra.I'm William.I'm using the SGMII IP core to connect my PC and the K7 board.And I really don't know the function of MDIO and auto-negotiantion option.Even after I read the UG047 twice.So can you tell me their function and how should I set these pins?By the way,I also don't know how to set the pins such as status_vector,configuration vector,speed_is_10_100. Now I need to instantiate two SGMII IP core. I really don't know what to do, so can you give an idea please?Thank you very much!

 Regards,William.

0 Kudos