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Observer
Observer
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Registered: ‎07-05-2018

sgmii ODDR clock for internal MAC

Form SGMII IP core sgmii_clk_r_0, sgmii_clk_r_0, sgmii_rx_clk_f_0, sgmii_rx_clk_r_0 are output using ODDR primitive sgmii_clk and sgmii_rx_clk clocks are generated.

 

from logic its looks like

1Gbps Ethernet operation         *r_0= 1 *f_0=0                                    output clock = 125MHz 

10Mbps Ethernet operation       *r_0= 1.25MHz  *f_0= 1.25MHz         output clock = 1.25MHz 

100Mbps Ethernet operation     *r_0= 12.5MHz  *f_0= 12.5MHz         output clock = 12.5MHz

 

if the mac is internal what is solution(logic) to replace ODDR.

 

 

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Moderator
Moderator
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Registered: ‎08-25-2009

Hi @apisal,

 

What do you mean the MAC is internal?

"Don't forget to reply, kudo and accept as solution."
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Observer
Observer
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Registered: ‎07-05-2018

As per GMII specification clock and data with specification is as below

                                    GMII spec                                                                       Xilinx IP spec

Speed                mac_rx_clk/mac_tx_clk  txd/rxd valid data width     sgmii_clk/sgmii_rx_clk txd/rxd valid data width

1000Mbps              125MHz                        [7:0]                                125MHz                               [7:0] 

100Mbps                 25MHz                         [3:0]                               12.5MHz                               [7:0]

10Mbps                   2.5MHz                        [3:0]                                1.25MHz                              [7:0]

 

 

as per IP core documentation this conversion need to be done in client logic. But this conversion take care by IP for Zynq device with MAC in Zynq PS option. For Xilinx TEMAC of Ultrascale(non zynq) device IP does not provide this option/conversion. 

 

following are description provided in 1G/2.5G Ethernet PCS/PMA or SGMII v16.0 LogiCORE IP Product Guide

Only when the core is connected to ENET0/1 in the Zynq-7000 AP SoC processor subsystem, the core takes care of
converting the 4-bit MII interface to the 8 bits required by the core. In all other cases the
core expects 8 bits from the client logic

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Observer
Observer
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Registered: ‎07-05-2018

Is it possible to port zynq sgmii IP with mac in ps option to non zynq FPGA. This configuration is only available in sgmii ip when zynq device is selected. I want to use same configuration in ultrascale+ device.

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