05-22-2016 06:59 PM
We need to use the Xilinx IP tri_mode_ethernet_mac.Simulation in Vivado has no problem, but when we export all the simulation files and try to run simulation by ncverilog in Linux, simulation fails with the message"protected code". And we found the simulation netlist of mac core is encrypted.
So do we have to purchase the full version license such that we can run simulation without Vivado? Or is there other way we counld get a free simulation netlist first?
We will buy the virtex-UltraScale VCU108 evaluation board, and do you provide some IP along with the board such as this ethernet mac IP?
05-22-2016 10:39 PM
Protected code errors will happed due to incompatible tools.
Please refer the release notes of the Vivado version you are using and use compatible third party simulation tools and you should be able to simulate the core.
05-30-2016 07:45 PM
We decide to run simulation in Vivado. So there is no problem now.
But there is another issue.
When I run "axi 1G/2.5G ethernet subsystem" example design, it can generate bitstream.
But when I create block design which includes this IP(axi 1G/2.5G ethernet subsystem),
it fails to generate bitstream(place & route no problem), with the message :
this design contains one or more cells for which bitstream generation is not permitted,
But the example design can generate bitstream,so I am confused.
Do you have idea to solve this?
05-30-2016 11:44 PM
What type license do you have(Full or Hw evaluation)
Try resetting the output products and regenerating the core again in block design if you generated the license recently, tool may have generated the core with design linking license.
06-14-2016 01:51 PM
I just bought a KC705 board and I tried to recompile the original BIST testcase (rdf0185-kc705-bist-c-2014-3) and I am getting the same error above. I am using the 2016.2 Vivado software. I was interested to run the entire flow with a proven example.
Shouldn't the KC705 license cover the IPs that are delivered with the testcase?
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: system_i/axi_ethernet_0/inst/eth_mac/inst/tri_mode_ethernet_mac_i/bd_4bad_eth_mac_0_core tri_mode_ethernet_mac_v9_0_5)
I have already tried to reset and regenerate the IPs....