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Adventurer
Adventurer
1,182 Views
Registered: ‎05-11-2018

tx_axis_mac_tdata and wireshark

Hello,

 

I opened the example design of the Tri Mode Mac Ethernet IP,  connected it to the SGMII ethernet IP then i implemented the design on a VC707 fpga card.

I opened wireshark and the softare captured 4 frames , corresponding to the four frames sent by the packet generator in the example design by Xilinx. 

The problem is that i can't manage to understand the link between the data on the tx_axis_mac_tdata and the data showed on the software wireshark.

My understanding of tx_axis_mac_tdata is the follwing; 

6 bytes of destination address  / 6 bytes of source address / 2 bytes Length / X bytes of DATA.

 

Here are the 3 frames sent on the tx_axis_mac_rdata:

 

Frame 1 :Destination Address : 5A 02 03 04 05 06

                   Source  Address : DA 02 03 04 05 06

                   Length : 00 2E

                 Data : 01 02 03 … 2C 2D 2E  

 

Frame 2 :Destination Address : 5A 02 03 04 05 06

                   Source  Address : DA 02 03 04 05 06

                   Length : 80 00

                 Data : 01 02 03 … 2C 2D 2E 2F

 

Frame 3 :Destination Address : 5A 02 03 04 05 06

                   Source  Address : DA 02 03 04 05 06

                   Length : 00 03

                 Data : 01 02 03

 

Here is what i see on wireshark::

 

Could anyone help me see through this

 

 

 

 

wireshark.png
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Moderator
Moderator
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Registered: ‎11-09-2017

Hi

 

Could you explain hardware test set up how you have connected to PC connections between board and PC.

Regards
Pratap

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Adventurer
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Registered: ‎05-11-2018

I have connected the PC to the VC707 using the ethernet cable.

The constraints of the board are the following:

#***********************************************************
# The following constraints target the Transceiver Physical*
# Interface which is instantiated in the Example Design.   *
#***********************************************************
#-----------------------------------------------------------
# Transceiver I/O placement:                               -
#-----------------------------------------------------------

# Place the transceiver components, chosen for this example design
# *** These values should be modified according to your specific design ***

set_property LOC GTXE2_CHANNEL_X1Y27 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i]



#-----------------------------------------------------------
# Clock source used for the IDELAY Controller (if present) -
# and for the transceiver reset circuitry                  -
#-----------------------------------------------------------


create_clock -name independent_clock -period 5.000 [get_ports independent_clock]

#-----------------------------------------------------------
# PCS/PMA Clock period Constraints: please do not relax    -
#-----------------------------------------------------------

create_clock -add -name gtrefclk -period 8.000 [get_ports gtrefclk_p]


#-----------------------------------------------------------
# Transceiver I/O placement:                               -
#-----------------------------------------------------------

# Place the transceiver components, chosen for this example design
# *** These values should be modified according to your specific design ***

#set_property LOC H6 [get_ports gtrefclk_p]
#set_property LOC H5 [get_ports gtrefclk_n]


#***********************************************************
# The following constraints target the GMII implemented in *
# the Example Design.                                      *
#***********************************************************
# The GMII is intended to be an internal interface.        *
# The GMII signals should be connected directly to user    *
# logic and all of the following constraints in this file  *
# should be removed.                                       *
#***********************************************************


#-----------------------------------------------------------
# Fast Skew maximises output setup and hold timing         -
#-----------------------------------------------------------
set_property SLEW FAST [get_ports {gmii_rxd[*]}]
set_property SLEW FAST [get_ports gmii_rx_dv]
set_property SLEW FAST [get_ports gmii_rx_er]

set_property PACKAGE_PIN AH7 [get_ports SYS_CLK_N]
set_property PACKAGE_PIN AH8 [get_ports SYS_CLK_P]

set_property IOSTANDARD LVDS [get_ports independent_clock_bufg_n]
set_property PACKAGE_PIN E18 [get_ports independent_clock_bufg_n]
set_property PACKAGE_PIN E19 [get_ports independent_clock_bufg_p]
set_property IOSTANDARD LVDS [get_ports independent_clock_bufg_p]

set_property PACKAGE_PIN AP40 [get_ports RESET]
set_property IOSTANDARD LVCMOS18 [get_ports RESET]

set_property PACKAGE_PIN AM39 [get_ports LED]
set_property IOSTANDARD LVCMOS18 [get_ports LED]

set_property PACKAGE_PIN AM7 [get_ports RXN]
set_property PACKAGE_PIN AM8 [get_ports RXP]
set_property PACKAGE_PIN AN1 [get_ports TXN]
set_property PACKAGE_PIN AN2 [get_ports TXP]

set_property PACKAGE_PIN AJ33 [get_ports PHY_RESET]
set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET]
#-----------------------------------------------------------
# GMII Transmitter Constraints:  place flip-flops in IOB   -
#-----------------------------------------------------------
#set_property IOB TRUE [get_cells gmii_txd*]
#set_property IOB TRUE [get_cells gmii_tx_en*]
#set_property IOB TRUE [get_cells gmii_tx_er*]

#-----------------------------------------------------------
# GMII Receiver Constraints:  place flip-flops in IOB      -
#-----------------------------------------------------------
#set_property IOB TRUE [get_cells gmii_rxd*]
#set_property IOB TRUE [get_cells gmii_rx_dv*]
#set_property IOB TRUE [get_cells gmii_rx_er*]




The SGMII IP is configured like the following:

config_sgmii_vc707.png
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Moderator
Moderator
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Registered: ‎11-09-2017

Hi

 

Please go through following link, packets captured in wireshark

https://www.xilinx.com/support/documentation/boards_and_kits/kc705/2013_4/xtp199-kc705-ethernet-c-2013-4.pdf

Regards
Pratap

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Adventurer
Adventurer
1,117 Views
Registered: ‎05-11-2018

My question is more about the sending of the packets of the example design of the tri mode mac IP on the ethernet line.

I wonder why i can't see them.

(I tried to follow the document but it refers to the KC705 i have the VC707)

I think the problem may come for the Mac clock

Actually i connected the gtx_clk of the tri mode mac to the output of the SGMII IP (rxuserclk2)

But i'm not sure it is correct.

Here are a few clocks that are outputed from the SGMII IP which one should i connect to  the MAC clock (gtx_clk)

On the IP documentation it is said to connect the mac clock to the userclk2 clock but that clock is not available on the wrapper of the example design of the SGMII IP. furthermore it stays at '0' for almost 3 ms on the simulation.

 

 

 

sgmii_clocks.png
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Moderator
Moderator
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Registered: ‎11-09-2017

Hi

 

Are you looking for simulation ?

 

Did you add logic analyzer to design?

 

Shared the ila dump, make sure following signals are included

 

tx_axis_mac_tdata,tx_axis_mac_tvalid,tx_axis_mac_tlast, tx_axis_mac_tuser, tx_axis_mac_tready

 

gmii_txd[7:0], gmii_tx_en, gmii_tx_er

Regards
Pratap

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Adventurer
Adventurer
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Registered: ‎05-11-2018

Hello,

 

I'm using the ILA also but i can't manage to make the trigger work. I will look into it

By the way do you know to which clock i should connect the gtx_clock of the tri modemac module?

rxuserclk2 gtrefclk_bufg_out and userclk2 have all the same frequency of 125 MHz but are phase shifted.

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Adventurer
Adventurer
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Registered: ‎05-11-2018

Hello,

 

So apparently the packets captured by wireshark are 4 ARP requests sent by my PC.

I added an ILA core to capture gmiirx_er , gmii_rx_dv and gmii_rxd(7 : 0) , i added a trigger on the rising edge of gmii_rx_dv.

But i never capture that moment.

The four ARP requests are sent by the PC whenever a activate PHY_RESET and then release it.

Here is the trigger capture by the ILA and the screen capture of wireshark:

By the way my design meets all the timing requirements.

I added a 200 Mhz clock constraint on independent_bufg and a 125 Mhz clock constraint for gtrefclk:

 

 

wireshark.png
ILA_trigger.png
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Moderator
Moderator
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Registered: ‎11-09-2017

Hi

 

userclk2 is connected to gtx_clk of TEMAC.

Regards
Pratap

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Moderator
Moderator
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Registered: ‎11-09-2017

Hi

 

ILA should be add on tx path rather then rx path.

 

In this use case you are looking to packet monitor in wireshark.

Regards
Pratap

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Adventurer
Adventurer
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Registered: ‎05-11-2018

I monitored on the rx path, because the ARP request are sent by the PC to the FPGA and not the opposite ( i was wrong in my initial post i thought that the 4 packets i had seen in Wireshark were from the FPGA packet generator but actually they come from the PC)

But i see no rising edge on gmii_rx_dv

 

(I'll try to send data from the MAC tri modeby asserting signal tx_axi_tvalid tx_axis_tdata and tx_axis_tlast and monitor the tx path on ILA )

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