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Visitor
Visitor
6,155 Views
Registered: ‎08-12-2008

xps_uartlite baud rate anomaly

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Hello all,

 

I am using the xps_uartlite with a microblaze on a Spartan3E and I am seeing some strange behavior related to Baud Rate.  I have triple checked, that the baud rate in my EDK design is set to 9600.  However, when I connect the device to a serial port on my PC (through an IOGEAR GUC232A USB to Serial Adapter) I get gibberish at 9600.  At 4800 the display is correct.  I have tested this using both TeraTerm and HyperTerm.  This behavior has persisted through several builds of the hardware/software.

 

I have NOT tried a new USB to Serial Adaptor, different FPGA, or different computer.

 

Has anyone else seen this behavior before?

 

Thanks,

Sean

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Visitor
Visitor
6,601 Views
Registered: ‎08-12-2008

Thanks for the reply timpe.

 

Although your suggestion didn't pinpoint the problem it did lead me to the solution.

 

I have a clock generator component in my design.  The input clk freq is 100 MHz but I had that output clk freq set to 50 MHz for some reason.  Once I set it to 100 MHz my problem was solved.

 

 

Sean

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Xilinx Employee
Xilinx Employee
6,153 Views
Registered: ‎08-13-2007

Sean,

The question may be better suited for the EDK and Platform Studio Board since this IP is distributed via that tool.

 

But I would check the C_SPLB_CLK_FREQ_HZ parameter in the mhs file - it should agree with your MicroBlaze/PLBv4.6 clock. The divisor for the baud rate is configured by the joint setting of the baud rate (C_BAUDRATE) and system clock (C_SPLB_CLK_FREQ_HZ). If you made changes to the system clock rate (e.g. new DCM confguration) but didn't change the clock rate, the effect could be like you've seen.

 

bt

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Visitor
Visitor
6,602 Views
Registered: ‎08-12-2008

Thanks for the reply timpe.

 

Although your suggestion didn't pinpoint the problem it did lead me to the solution.

 

I have a clock generator component in my design.  The input clk freq is 100 MHz but I had that output clk freq set to 50 MHz for some reason.  Once I set it to 100 MHz my problem was solved.

 

 

Sean

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Xilinx Employee
Xilinx Employee
6,118 Views
Registered: ‎08-13-2007

That makes sense. The clock generator modules uses a DCM to generate the clock. If the embedded system was originally configured for 100MHz, the UART would be configured accordingly originally. If the clock generator's output was changed for some reason later to 50MHz, the effect would be as you described to the UART. You could fix this from the UART's perspective by reconfiguring the UART as described above or by changing the clock back. Though there are obvious differences in the embedded subsystems performance and the FPGA's dynamic power between the two approaches.

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