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Adventurer
Adventurer
530 Views
Registered: ‎11-26-2018

zcu106 10G ethernet subsystem critical warning

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Hi,

I'm trying to use the 10G ethernet subsystem, but I have a critical warning during the implementation:

CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
design_1_i/design_1_i/xxv_ethernet_0/inst/IBUFDS_GTE4_GTREFCLK0_INST
user_si570_sysclk_clk_n
user_si570_sysclk_clk_p
 CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
design_1_i/design_1_i/xxv_ethernet_0/inst/IBUFDS_GTE4_GTREFCLK0_INST
user_si570_sysclk_clk_n
user_si570_sysclk_clk_p

I don't know how to solve it.

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Adventurer
Adventurer
453 Views
Registered: ‎11-26-2018

Solved selecting custom gt_ref_clk in the eth subsystem IP

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2 Replies
Xilinx Employee
Xilinx Employee
495 Views
Registered: ‎09-05-2018

Hey andrea@ross,

What constraints have you applied to those ports, is there anything in your constraints file? And which part are you targetting? You might try checking or replacing the pins.

Did you start with the IP Example Design?  

Nicholas Moellers

Xilinx Worldwide Technical Support
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Adventurer
Adventurer
454 Views
Registered: ‎11-26-2018

Solved selecting custom gt_ref_clk in the eth subsystem IP

View solution in original post

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