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Observer jasbir229
Observer
626 Views
Registered: ‎11-13-2018

How to access XADC using FPGA logic via DRP Port on ZC 706 Board

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Hello Mentors,

I'm using ZC706 eval board. I need to access XADC via DRP port using FPGA logic. Please suggest, how can i do this using fpga logic and drp only. 

Please let me know, how to connect DRP port signals(Den, Daddr[6:0], DI,DO,DCLK,DRDY,DWE etc) to fpga logic (General connection type) and how can i debug XADC using Vivado integrated logic analyser.

In short i want to access XADC using fpga via drp and want to analyse on vivado integrated logic analyser.

Thank you.

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1 Solution

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Moderator
Moderator
592 Views
Registered: ‎08-08-2017

Re: How to access XADC using FPGA logic via DRP Port on ZC 706 Board

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Hi @jasbir229

The DRP detailed timing is 

Capture.PNG

DCLK , DEN , DWE, DADDR and DI signals to be driven from FPGA logic.  You need to write your own FSM depending on which registers you want to read or which parameter you want to alter dynamically.

The example design instantiation in UG480 (page83) is useful in writing your own FSM.  The first step should be to simulate the Example design in user guide and then change the FSM as per your application.

To test on the Hardware, as you mentioned , you need to insert the ILA core in the design , run ILA either on DCLK or faster clock (if you want to monitor DCLK) and assign the DEN, DWE, DADDR, DI inputs to the XADC and DO, DRDY, EOS/EOC, Busy and channel_out outputs from XADC to the ILA ports.

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Reply if you have any queries, Give Kudos and accepts as Solution

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Reply if you have any queries, give kudos and accept as solution
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2 Replies
Moderator
Moderator
593 Views
Registered: ‎08-08-2017

Re: How to access XADC using FPGA logic via DRP Port on ZC 706 Board

Jump to solution

Hi @jasbir229

The DRP detailed timing is 

Capture.PNG

DCLK , DEN , DWE, DADDR and DI signals to be driven from FPGA logic.  You need to write your own FSM depending on which registers you want to read or which parameter you want to alter dynamically.

The example design instantiation in UG480 (page83) is useful in writing your own FSM.  The first step should be to simulate the Example design in user guide and then change the FSM as per your application.

To test on the Hardware, as you mentioned , you need to insert the ILA core in the design , run ILA either on DCLK or faster clock (if you want to monitor DCLK) and assign the DEN, DWE, DADDR, DI inputs to the XADC and DO, DRDY, EOS/EOC, Busy and channel_out outputs from XADC to the ILA ports.

----------------------------------------------------------------------------------------------------------------------------------------------------------------------

Reply if you have any queries, Give Kudos and accepts as Solution

-------------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
0 Kudos
Observer jasbir229
Observer
575 Views
Registered: ‎11-13-2018

Re: How to access XADC using FPGA logic via DRP Port on ZC 706 Board

Jump to solution

Hello @pthakare

Thank you for your reply.

I Follow the Example Instantiation from UG480. I used the instantiation only for VP& VN external inputs. I applied a DC voltage at the VP(+) & VN(-).  Now imI facing the problems as follows in berie:

1. [15:0] do_drp = 0000 always (ILA waveform)

2. DRDY= logic 0 always(ILA waveform)

3. Tcl console : debug core has no free running clock. 

I have attached a word file herewith. Please refer the attachment for code used, Error ocurreoc, Messages, Tcl console messages. 

I don't understand that from where I can get the XADC sampled data via DRP port.

Thank you.

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