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Visitor gopal@123
Visitor
94 Views
Registered: ‎04-01-2019

Preserve design

Hi everyone,

When I am implementing a TDC carry chain alone it is showing an equal propagation delay after each element which is desired, but when I am implementing a same TDC carry chain module with the combination of counter it is giving different timing results, the propagation delay is different after each delay element. So, I want to preserve the desired timing reading in combined (counter + carry chain) implementation,same like carry chain alone implementation. Please any one has idea how to preserve design please answer. I am using vivado 2018.3 with artix 7 FPGA.

 

Thanks,

Gopal.

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7 Replies
Scholar drjohnsmith
Scholar
86 Views
Registered: ‎07-09-2009

Re: Preserve design

I have feeling here your fighting the tools, and will not win.

Why do you need to manualy craft a carry chain counter ?

in vhdl we would do A <= A + 1;

 

The tools work to impliment your logic, in such a way that it meets the timming constraints.

rember also the tools will modify your code to meet timming, whilst keeping the same function,  

Its like trying to program in say C against the register level of the processor.

    you could program at the direct register level, but do you need to ?

 

whats your programing language ?

 

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Visitor gopal@123
Visitor
71 Views
Registered: ‎04-01-2019

Re: Preserve design

@drjohnsmith 

Sir I am using verilog HDL and trying to implement TDC in FPGA artix7. I am new to vivado and FPGA.

 

Thanks,

Gopal.

 

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Scholar drjohnsmith
Scholar
66 Views
Registered: ‎07-09-2009

Re: Preserve design

Ok,

 

so your implimenting a delay unit,

   probably used for an oscilator I guess.

there are a few optoins if this is so

https://www.xilinx.com/support/documentation/application_notes/xapp872.pdf

https://forums.xilinx.com/t5/Other-FPGA-Architectures/Ring-Ocillator-Nexys-4/td-p/625227

 

 

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Visitor gopal@123
Visitor
60 Views
Registered: ‎04-01-2019

Re: Preserve design

@drjohnsmith 

Sir, this is not for oscillator, it is for Time to Digital Converter(TDC). 

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Visitor gopal@123
Visitor
53 Views
Registered: ‎04-01-2019

Re: Preserve design

@drjohnsmith 

I am instantiating one module in the another one(main project).

Before instantiating in the main project its timing propagation works fine when it is implemented alone, but after instantiating in main project its timing propagation deviating from the previous one. I think before instantiating I have to "Preserve Design". If you have about it please give me a reply.

 

Thanks,

Gopal.

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Scholar drjohnsmith
Scholar
40 Views
Registered: ‎07-09-2009

Re: Preserve design

Visitor gopal@123
Visitor
22 Views
Registered: ‎04-01-2019

Re: Preserve design

@drjohnsmith 

Sir It was helpful. Thank you, for your overwhelmig respose. I am really very happy because the people like you are there in the community who repply very quickly ,so one can have expectation from the xilinx community of quick reply.

 

Thank You,

Gopal.

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