04-23-2019 11:24 PM
When I am implementing a TDC carry chain alone it is showing an equal propagation delay after each element which is desired, but when I am implementing a same TDC carry chain module with the combination of counter it is giving different timing results, the propagation delay is different after each delay element. So, I want to preserve the desired timing reading in combined (counter + carry chain) implementation,same like carry chain alone implementation. Please any one has idea how to preserve design please answer. I am using vivado 2018.3 with artix 7 FPGA.
04-24-2019 12:41 AM
I have feeling here your fighting the tools, and will not win.
Why do you need to manualy craft a carry chain counter ?
in vhdl we would do A <= A + 1;
The tools work to impliment your logic, in such a way that it meets the timming constraints.
rember also the tools will modify your code to meet timming, whilst keeping the same function,
Its like trying to program in say C against the register level of the processor.
you could program at the direct register level, but do you need to ?
whats your programing language ?
04-24-2019 06:21 AM
so your implimenting a delay unit,
probably used for an oscilator I guess.
there are a few optoins if this is so
04-24-2019 06:52 AM
I am instantiating one module in the another one(main project).
Before instantiating in the main project its timing propagation works fine when it is implemented alone, but after instantiating in main project its timing propagation deviating from the previous one. I think before instantiating I have to "Preserve Design". If you have about it please give me a reply.
04-24-2019 08:42 AM
04-24-2019 09:33 PM
Sir It was helpful. Thank you, for your overwhelmig respose. I am really very happy because the people like you are there in the community who repply very quickly ,so one can have expectation from the xilinx community of quick reply.