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Newbie rosevall
Newbie
6,937 Views
Registered: ‎10-06-2009

SP601 Reference Design

Hi,

 

I have just obtained a SP601 evaluation kit for spartan-6. However i cannot find the source code for the reference design already loaded on the board Flash memory.  In the FAQ for the board (dated June 24 2009) it is written that soon there will be made available a "Base Reference Design - demonstrates board functionality and provides a reference design and tutorial demonstrating how to download, modify and customize a design".

 

Does anyone know if it has been released yet or if it will be soon? 

 

I have found some reference material at http://www.xilinx.com/products/boards/sp601/reference_designs.htm  but it is mainly C-code. Will there be VHDL/Verilog code made available for the board reference design?

 

/John

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6 Replies
Visitor mtisza
Visitor
6,811 Views
Registered: ‎10-18-2009

Re: SP601 Reference Design

I'm looking for the same thing.  The HDL sources for the board.  Specifically the TEMAC IP core it uses.  Does anyone knwo where it is avialable and if it is?
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Visitor thomas66
Visitor
6,626 Views
Registered: ‎12-05-2009

Re: SP601 Reference Design

The rdf0003.zip has changed and now contains all the sources for the reference design demonstarting the DSP.

However, I was unable to locate the source files for the BIST demo.  rdf0045.zip contains all the C-cod, there isn't a single vhdl nor verilog!

 

I am especialy interested how the UART-USB got hooked up in the fibric.#

 

Thanks,

Thomas

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Xilinx Employee
Xilinx Employee
6,619 Views
Registered: ‎01-03-2008

Re: SP601 Reference Design

The BIST design uses an EDK design flow and the MHS file is provided for this system in the rdf0045.zip file.  There isn't any extra HDL code required.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Observer lisafu
Observer
6,132 Views
Registered: ‎04-08-2010

Re: SP601 Reference Design

Hi, mcget:

 

        I have sp601 and WebBack (which doesn't not include EDK). Since Xilinx claims that sp601 doesn't require other design tools (those fancy tools do have nice feature I believe, but with extra bucks.), then why Xilinx doesn't provide reference design for sp601 customer who has only WebPack? I have seen another example (SP601 MIG Design Creation, xtp039) needs ChipScope (again, WebPack doesn't include this). It looks like that there is a few reference design left for sp601 user who only has WebPack without paying extra design tools.

 

        I have found two copies of XTP039 documentation. One is "SP601 MIG Design Creation" and the other is "SP601 DDR2 Memory Demonstration". The former needs ChipScope and I can't continue to follow this tutorial. It looks like the later doesn't need ChipScope, but there is no rdf0005.zip to accomany this.

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Visitor cwavnew
Visitor
5,463 Views
Registered: ‎09-07-2010

Re: SP601 Reference Design

HELP!  The SP601 MIG Design example uses (requires) the Chipscope Pro.

 

I don't have this tool and therefore can not build the bitstream.  I don't need the prebuilt one since I will want to make changes to this project for evaluation.

 

How do I get to a version of this project that does not require the Chipscope Pro to build?

 

I am evaluating the Spartan6 to see if the memory interface will perform as I need in our design, and I'm not about to drop $1K on the Chipscope unless it works.

 

 

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Visitor cwavnew
Visitor
5,459 Views
Registered: ‎09-07-2010

Re: SP601 Reference Design

OK, so I got the 30-day evaluation version of the ISE tools which includes the Chipscope Pro which should be more than enough time to determine if the part will work for us...

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