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Visitor stfrha
Visitor
15,184 Views
Registered: ‎05-14-2012

VC707 with Ethernet

Hello

 

Have anyone succeeded in implementing ethernet (using AXI4-stream FIFO) on the VC707? I am using 13.4 and did soon realized that the tool doesn't give me the same support as it do for the ML605 board. I can not create a template design with ethernet.

 

There is not any example design source code available from xilinx either. Only a bit-file with a readme that says that I should look into another design (the BIST with its document xtp140.pdf) for ethernet source code. But in this document (or design files) there is no ethernet source or information.

 

However, I have made a manual design using ISE/EDK/SDK and created a peripherial test projet. The thing start but freezes when the the ethernet/FIFO-combo is taken out of reset. As far as I understand, the ethernet core does not start.

 

Any ideas?

 

/Fredrik

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43 Replies
Visitor stfrha
Visitor
15,181 Views
Registered: ‎05-14-2012

Re: VC707 with Ethernet

Also, I have tested the example ethernet bit-file and it seems to work, so the HW seems to be okey.
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14,930 Views
Registered: ‎09-14-2012

Re: VC707 with Ethernet

Hello Frederik,

 

we're also trying to implement the 1GbE interface in the VC707.


We tested the Xilinx provided bitfile, everything is fine. But as you say: there is no source code to verify...

 

As we had designs making use of the tri-mode-ethernet (running 1GbE) on ML507 and ML605 using gmii with the Xilinx core for us was doable.

 

Now on VC707 everything seems to be different.

 

Currently we're trying to set up the 1000BASE-X PCS/PMA core, using the SGMII interface.

 

Simulations of that core design at 1Gbit fail, 100Mbit seems to work.

 

Can anybody explain? Does anyone have any experience or the same problems?

 

Best regards, Steffen

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Visitor mbuccier
Visitor
14,727 Views
Registered: ‎10-16-2012

Re: VC707 with Ethernet

Has anyone had any luck with this issue?

 

I am using the BIST ISE 14.2 example design for the VC707.  I had to connect the 'GTX_CLK' signal of the axi_ethernet module to bring the PHY out of reset.  But the TX LED on the PHY is not active.

 

When I use an axi chipscope monitor on the receive axi streams from the ethernet controller to the axi dma, the resets are not active.  However, when I try to ping the FPGA, none of these signals change value.  I am assuming the axi ethernet controller is still in reset for some reason or a clock is not being provided properly.

 

Thanks, Mark

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Adventurer
Adventurer
14,563 Views
Registered: ‎01-28-2008

Re: VC707 with Ethernet

I am also trying to get an SGMII core to work on the VC707 board with a MicroBlaze design.  I noticed the BIST design has an ethernet core, but there are no sample applications for it.  Has anyone had any success integrating SGMII with a MicroBlaze system and using the SDK to run something like their Light Weight IP (LwIP) or transfering data to the FPGA via Ethernet?

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Visitor lamiastella
Visitor
14,377 Views
Registered: ‎11-28-2012

Re: VC707 with Ethernet

How did you find the ucf file for VC707? Also in the manual it is not mentioned where the pins like PHY_DRX....and PHY_DTX ...and PHY_COL should be connected! Do you know how to handle that? I am using XPS 14.3!

 

Please let us know what's the solution for this!

Where can I find a working ucf for Ethernet?

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Visitor stfrha
Visitor
14,296 Views
Registered: ‎05-14-2012

Re: VC707 with Ethernet

I started a web-case in May. They (Xilinx) told me that the source code for the example design was "not trivial" and they recomended using the EDK environment to implement an Ethernet solution. This is fine by me but I still could not get the EDK projects to work. I started a new webcase and this has been pending since then.

Now (friday, december 21, more then six month later) got a EDK/SDK project that was verified to work by Xilinx on the VC707. I am not sure but I think it includes some updated IP-blocks of the Axi 10/100/1000 MAC and the Axi4 Stream DMA component controlled from a Microblaze. The IP source code show traces of debugging.

Initial tests on my end this friday showed no success but I will work more with it an let you know.

We (our company) have built other Virtex7 HW and not been able to get Ethernet working on these either. It beginning to be a big issue for us now.
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Visitor stfrha
Visitor
14,297 Views
Registered: ‎05-14-2012

Re: VC707 with Ethernet

lamiastella: The ucf file is included in the documentation supplied with the VC707 card. The signals you refer to is related to the GMII interface (I think) which is not used by the card. I think this is the reason these signals are not included in the UCF (if they are left out, I mean. I haven't checked.)

 

A full schematics for the board (a pdf) is also supplied and any signals that may be missing in the UCF could be found there. However, I would bet that the GMII-specific signals is not available on the card.

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Observer berkbasaklar
Observer
14,270 Views
Registered: ‎01-04-2011

Re: VC707 with Ethernet

I have been working on this issue for about 3 weeks. My observation is that axi_ethernet with SGMII interface somehow does not activate the mgts even though from the status registers it says that MGT's are ready and everything is well met for the transmission. 

 

I have been trying with ISE ver 14.4 but still no response to the lwip echo server application. All the initilizations speed settings are well done but what I saw is that the gratious ARP from the board does not come out from the PHY as I am monitoring through the Wireshark. This I guess again is related to the Axi_ethernet IP with SGMII interface configuration.

 

Hope Xilinx can find a quick fix for this. 

 

Best regards,

Berk

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Visitor stfrha
Visitor
14,235 Views
Registered: ‎05-14-2012

Re: VC707 with Ethernet

I have tried the a design that Xilinx claims work on Rev B of the VC707. The design consists of a pre-build bit-file and two SDK projects. One is a peripherial test and the other is a (pingable) Echo server. I can not make this work on my card, however. I have tried to do a design using 14.4 and get the same result.

 

In all cases the SDK projects fail at the same function. It is during intitilization of the Axi Ethernet the MAC IP does not seem to leave reset and after a timeout an assert is failing.

 

Will post more if I have some progress.

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Observer berkbasaklar
Observer
12,230 Views
Registered: ‎01-04-2011

Re: VC707 with Ethernet

I am still at the same point no progress regarding to the axi_ethernet with SGMII and with Microblaze. However I have managed to get a communication done with pure FPGA logic using tri_mac_ethernet core and gig_eth_pcs_pma core on VC707 and on my custom design board. This proves that the hardware is correct for SGMII communication. However for functional use I have to run TCP/IP, and for that I have to run lwIP with the AXI_ethernet which is the case that I am stuck in.

 

Will post if I have any progress.  

 

Best regards,

Berk

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Visitor ascaminaci
Visitor
12,209 Views
Registered: ‎08-01-2012

Re: VC707 with Ethernet

I'm in the same boat. I need the lwIP example running to prove connectivity and have also experimented with my own MHS wiring based on the KC705 board base system but to no avail. The VC707 uses a new serial chip rather than an 8-bit GMII interface like the other Xilinx dev boards and my belief is that there is some configuration issue in setting up the transceivers for SGMII functionality. Or, it might be communication between the tri-mode MAC and the transceiver that's not working correctly. As of ISE 14.4, Xilinx still does not support a base system build including ANY ethernet interface.

 

What I don't understand is how they can send out working bit files but no MHS/UCF files so we can duplicate this ourselves. What good is their working bit file if we can't build our own system around their working example? Why won't Xilinx release the source files for the working bit files they have available?

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Moderator
Moderator
12,176 Views
Registered: ‎08-10-2007

Re: VC707 with Ethernet

All,

 

Are you aware of (Xilinx Answer 46384): http://www.xilinx.com/support/answers/46384.htm?

 

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Observer berkbasaklar
Observer
12,164 Views
Registered: ‎01-04-2011

Re: VC707 with Ethernet

Hi, 

 

I am aware of this solution but it seems to be a solution for ethernet interface without Microblaze. When axi_ethernet is used as it is a licensed core, there is no access to the source files which implies that we cannot apply the same solution to this particular case. 

 

Best regards, 

Berk

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Visitor pi-xel2000
Visitor
12,118 Views
Registered: ‎01-28-2013

Re: VC707 with Ethernet

Hello!

 

I am working with AXI Ethernet in 1000MBit Soft TEMAC SGMII mode on VC707 board and got some partial success. I connect the AXI Ethernet to AXI DMA and use it alongside a Microblaze with Linux running on it.

 

When I disable AN, I notice that I can send packets correctly, but reception does not work well: Most of the received frames are dropped by AXI ethernet internally and the packets that come through have some bit errors.

 

When disabling dropping of bad frames, all received frames come through but have even more bit errors, alongside with wrong packet lengths.

 

That the frames are dropped inside AXI Ethernet already suggests that the problem lies in between PHY and AXI Ethernet, but not within the AXI streams or DMA.

 

I already tried the same setup on different boards, with different cables and different ethernet devices on the other side of the link, so that I can exclude faulty hardware.

 

Am I missing something? Maybe some additional constraints? Has someone got to a similar problem? Or has anyone already got a working setup for AXI Ethernet on VC707 board?

 

Thanks in advance!

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12,078 Views
Registered: ‎01-30-2013

Re: VC707 with Ethernet

Hi all, we are also having trouble getting axi_ethernet to run on the VC707 with its SGMII PHY connection (Marvell 88E1111). 2 issues, I did not see in this thread so far: 1. The communication with the PHY on the MDIO bus via axi_ethernet does not seem to work correctly, since reading the PHY's MII register 2 and 3 does NOT show a Marvell ID - they just return both 0 . Other MII registers return kind of valid values, but some are very strange: for example register 1 often returns 0x0148, which would mean that the PHY does not support e.g. 100/full, right? We hacked the Linux driver to return the usual Marvell 88e1111 ID (0x1410cc0), instead of the 0 ID to just make it continue using the marvell.c PHY driver. Looking at what the Linux marvell.c driver reads/writes from/to the PHY suggests that (again) that something is really wrong, because certain bits are set - but on a read after a write these bits do not seem to have changed. 2. The other thing, which does not look correct - at least to us, is that (at least on the VC707 we are looking at) R456 and R455 (below the Marvell chip) are MISSING. These two determine CONFIG4 of the Marvell Chip. However without them, CONFIG4 is floating, which does not seem to be correct. CONFIG4 determines most bits of HWCFG_MODE within the Marvell chip and thus decides which interface the chip should use (SGMII, RGMII, ...). Any comments? Did we overlook something?
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Observer berkbasaklar
Observer
11,986 Views
Registered: ‎01-04-2011

Re: VC707 with Ethernet

Hi everyone, 

 

I have come to solution where I have succesfully get the axi_ethernet working in SGMII mode with Microblaze. 

I have been in contact with Xilinx for about a month and at last we have come to an solution. 

 

The solution is that you have to update the axi_ethernet core and the lwip drivers with the Xilinx patched ones.

 

After that by using these core and driver by putting them in the repository, compile all the design again and finally you will get a working ethernet with lwip in SGMII mode.

 

I am sending out the patches below named as reporsitory. This includes lwip drivers and axi_ethernet core. 

 

I hope this will fix it for you. 

 

Best regards,

Berk 

 

 

 

Visitor eslitvak
Visitor
11,960 Views
Registered: ‎01-28-2013

Re: VC707 with Ethernet

Thank you!!!!!

 

It really works!

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Observer pnumer
Observer
11,919 Views
Registered: ‎07-16-2008

Re: VC707 with Ethernet

Thanks for the post Berk.  I'm a little new to this and having some issues with the proper connections to the IP.  Could you share the relavent parts of your mhs so I can see how you connected everything?

 

thanks

p

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Observer zhaochunming
Observer
11,914 Views
Registered: ‎12-14-2008

Re: VC707 with Ethernet

    Thanks for the post Berk. Any comment about the Config 4 pin? According to the datasheet of MAX88E1111, this pin shouldn't be left float. But in VC707 board it does. The status of Config 4 pin doesn't matter?

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Observer pnumer
Observer
11,655 Views
Registered: ‎07-16-2008

Re: VC707 with Ethernet

I added an axi_dma to connect to the axi_ethernet and  was able to build the system.  But I ran into trouble when I tried to use lwip; the program would hang at lwip_sock_init.

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Newbie gastebois
Newbie
11,638 Views
Registered: ‎02-21-2013

Re: VC707 with Ethernet

 
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Newbie gastebois
Newbie
11,636 Views
Registered: ‎02-21-2013

Re: VC707 with Ethernet

Hello,

 

Here same as joackinm@missing : problem while reading MDIO (get 0 in regs 2 and 3) often 0x148 in reg 1....

Has anyone a solution for that.

 

I tried without success the berkbasaklar's patch... Can you provide mhs/ucf ??

 

Thank you

 

Regards

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Visitor eslitvak
Visitor
11,632 Views
Registered: ‎01-28-2013

Re: VC707 with Ethernet

Hi, all.

 

I took Xilinx BIST example for ISE 14.1. It has right architecture of microprocessor system (axi_ethernet and dma instantation - what you asks). Changed it to SGMII. This project has error in clock_generator, correct it.

So I updated cores and lwip with Berk's files, created LwIp application and corrected it with raw example from xapp1026. It works.

 

Try this way!

Visitor pi-xel2000
Visitor
11,548 Views
Registered: ‎01-28-2013

Re: VC707 with Ethernet

Hello!

 

For those interested in getting axi_ethernet working alongside with Linux, I have just worked it out.

 

I also had the same problems with the inconsistent outputs of the PHY registers that return 0 (0x2 and 0x3) and 1 (0x4). But even if the read values are wrong, writing to those registers has an effect.

 

I haven't bothered with using the Marvell PHY driver, but put some dirty hacks into the generic one.

 

For reference, I attach my MHS file, as well as the modified versions of xilinx_axienet_main.c and phy_device.c.

 

Good luck!

 

PS: If it still does not work, you should look for some application to test whether the ethernet hardware is actually working correctly. I have spent almost 2 months working on a broken board (rx was broken), as the Xilinx Ethernet reference design is no use for verifying correct functionality.

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Visitor joft.mle
Visitor
11,468 Views
Registered: ‎01-31-2013

Re: VC707 with Ethernet

Hi all,

 

just wanted to let you know my findings on this vc707 + axi_ethernet issue since my last post (joachim@missinglinkelectronics.com).

 

Please note, that I did not follow this thread in last weeks and so I didn't have a chance to test/try berkbasaklar and

pi-xel2000 patches/files.
 
Regarding the issue not being able to really communicate with the Marvell PHY: I kind of overlooked that the axi_ethernet itself cannot do SGMII directly, but only with a kind of internal PHY attached to. This internal PHY also does have a MDIO interface and the axi_ethernet's MDIO controller is attached to both, this internal PHY and the external PHY, the Marvell on the VC707. This internal PHY is what we READ, if we issue a read on MDIO. It seems like the internal PHY "overrides" the signal coming from the Marvell PHY. I realized this while browsing through the axi_ethernet datasheet, it says that this internal SGMII PHY has the Vendor ID 0 => MDIO reg 2 & 3 == 0  .
 
@pi-xel2000: So it is interesting news to me, that writing actuallly works.
 
Next: The internal PHY also has an address - has to have, of course. This address seems to be 7 by default (C_PHYADDR), after adding an axi_ethernet with SGMII - at least in my case. However the Marvell on the VC707 is hard-coded to address 7, too - as we all know I guess. So I tried to set it to something different - I tried 1 - without success. I do not remember completely, but after setting it to 1, reads from address 7/Marvell still got "overridden" or I couldn't read anything anymore (0xffff).
So what I did: I disconnected the Marvell PHY from axi_ethernet and connected to a custom MDIO master.
 
After this very annoying discovery, the next issue is, that the internal PHY has the "isolated" bit set by DEFAULT, bit 10, reg 0 !! I don't get this. Why would anybody chose "off" as the default state of a networking PHY?
 
So after switching on the internal PHY, the whole thing starts to work. My current problem is: Often, after switching ON the internal PHY by clearing the "isolate" bit, the internal PHY's link just does not come up (bit 2, reg 1). And often, after this occurs, doing a reset (bit 15, reg 0) or just restarting auto-neg (bit 9, reg 0) does not bring up any link.

My gut feeling is, that this is a timing issue - regarding internal PYH register accesses, it seems like I get more stability (= link up more likely), if I include debug statements ;-) ...
 
This is my current state and I kind of stopped working on it, since we need axi_ethernet only while development for a other project.
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Newbie gastebois
Newbie
11,381 Views
Registered: ‎02-21-2013

Re: VC707 with Ethernet

Hello,

 

Quite the same for me here. I build my system using C_PHYADDR = 1 as my physical PHY address is 7. Now, I can read/write both PHY correctly.

 

BUT reseting the isolate bit has no effect. Effectively, the link status bit (internal PHY reg 1 bit 2) sometimes is 1, sometime 0.

 

Is it possible to do a loopback like : RJ45-> ext PHY -> int PHY-> ext PHY -> RJ45 to validate communication between FPGA and ext PHY ?

 

Regards

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Visitor spiderlux
Visitor
11,319 Views
Registered: ‎04-08-2013

Re: VC707 with Ethernet

Hi berkbasaklar, thanks for the files you uploaded. Can you help me also with the UCF file? As someone already said before, the UCF file produced by ISE for the VC707 board doesn't contain the LOC assignments for the Ethernet plug.

Did you get (or write) a working UCF with such assignments?

 

Thanks,

 

Regards

 

Luciano

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Visitor gran4341
Visitor
11,294 Views
Registered: ‎04-10-2013

Re: VC707 with Ethernet

Check out page 37 of the VC707 user guide for the pin locations. It doesn't list the I/O standards, though, but I'm sure you can figure out an appropriate choice from the Marvell documentation. These assignments are in the master UCF file, but you do need to go digging through for the proper names, which are not the same as the default names generated in XPS.

 

 

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Visitor spiderlux
Visitor
11,282 Views
Registered: ‎04-08-2013

Re: VC707 with Ethernet

From the VC707 manual I can see that the data buses (both rx and tx) between the FPGA and the Marvell device are serial differential lines, even if the remaining connections are ethernet signals. In EDK there is no Ethernet IP managing a serial connection with a PHY device. The only IPs I can find between the standard repository are:

 

- AXI Ethernet embedded IP v.3.01.a (two 8-bit data buses for rx and tx data)

- AXI 10/100 Ethernet MAC Lite v.1.01.a (two 4-bit data buses for rx and tx data)

 

There isn't any other Ethernet MAC controller I can use...

Moreover, if I wanted to create a custom EDK IP to manage the communication between FPGA and the Marvell device I would need at least the communication protocol technical specification (but it would be much more better the Marvell PHY device manual). Unfortunately such manual is not available online, on the Marvell website. You can download only the "product brief" pdf, that is a poor documentation, of course (here it is the link).

 

I opened a webcase, let's see what will happen...

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