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Visitor jmitch47
Visitor
3,194 Views
Registered: ‎06-15-2017

VCU 118 Limited PCIe

I have just started to work with the Xilinx VCU 118 evaluation kit with the Virtex Ultrascale+ VU9P FPGA (Engineering Sample). 

 

The card is installed in a Dell Precision 7910 workstation in slot 2 - a full PCIe 3.0 (8 GT/s) 16x slot. However, I am unable to get a design to successfully work above a PCIe 2.5 GT/s 4x link. I have tried the provided Xilinx PCIe 3.0 16x project and even the pre-generated bitfiles. I have also tried using Vivado 2016.4 and Vivado 2017.1 to no avail. Moving the card to a different slot seems to also have no effect. The issue appears to be a link training issue in the FPGA. 

 

Any thoughts on why this may be happening or advise on how to resolve this? The board is much less useful without proper high speed communication. 

 

Thanks for any help... 

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3 Replies
Scholar austin
Scholar
3,186 Views
Registered: ‎02-27-2008

Re: VCU 118 Limited PCIe

jm,

 

Per the Dell manual, support of PCIe slots requires a 2nd processor (option) for some features/speeds/slots.  Have you checked your machine was properly ordered to support the slot(s) you are trying to use?

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor jmitch47
Visitor
3,179 Views
Registered: ‎06-15-2017

Re: VCU 118 Limited PCIe

Yes, I am using both CPU sockets with Intel E5-2690 v4 CPUs. This PCIe slot does work as it previously was used for an nVidia P6000 GPU, and the motherboard silk screen shows it is a full PCIe 3.0 16x slot. I did try Slot 4 just for sanity, but I do not believe that had any effect.

 

It also does work in the slot if I configure the PCIe Core to only attempt to run 2.5 GT/s 4x. However, I cannot see the device at all in lspci or in the logs if I configure the board for its specified 8.0 GT/s at 16x (or even 2.5 GT/s 8x for that matter). 

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Scholar austin
Scholar
3,177 Views
Registered: ‎02-27-2008

Re: VCU 118 Limited PCIe

jm,

 

I suggest you contact your local Xilinx or authorized distributor, and request field support.  It should work with the (unmodified) reference design.

Austin Lesea
Principal Engineer
Xilinx San Jose
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