UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie gdawson
Newbie
7,759 Views
Registered: ‎01-24-2015

What IO standard is necessary to use JXADC port on Nexys 4 Board?

Hello all,

 

I'm trying to instantiate a design using the XADC wizard and I am having some trouble with the implementation of my verilog file. I have read through the user guides for the core wizard and the XADC on the 7 Series FPGA chips. I understand how to use the core, but syntehsis seems to be eluding me.

 

I am using the core in single channel mode, measuring the differential Vp/Vn voltage. Timing is set for continuous and I am trying to connect differential inputs over the JXADC pmod port. My current xdc constraints for this port are as follows:

 

#Pmod Header JXADC
#Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15,       Sch name = XADC1_P -> XA1_P
set_property PACKAGE_PIN A13 [get_ports {JXADC_P[0]}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {JXADC_P[0]}]
# /* other pins on port commented out */
#Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15,       Sch name = XADC1_N -> XA1_N
set_property PACKAGE_PIN A14 [get_ports {JXADC_N[0]}]				
	set_property IOSTANDARD LVCMOS33 [get_ports {JXADC_N[0]}]
# /* other pins on port commented out */

Synthesis step runs fine, but midway through my implementation run, I receive the following pop-up warnings:

 

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance SYS/xadc_wiz_0/inst/AXI_XADC_CORE_I/XADC_INST on site ILOGIC_X0Y132. The location site type does not match the instance type. Instance SYS/xadc_wiz_0/inst/AXI_XADC_CORE_I/XADC_INST belongs to a shape with reference instance JXADC_P_IBUF[0]_inst. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. [**/Nexys4_Master.xdc:325]
Resolution: Verify the location constraints for differential ports are correctly specified in your constraints. The Site type should be of form: IO_LxxP for P-side, and IO_LxxN for N-side (Neg Diff Pair)

[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance SYS/xadc_wiz_0/inst/AXI_XADC_CORE_I/XADC_INST on site ILOGIC_X0Y132. The location site type does not match the instance type. Instance SYS/xadc_wiz_0/inst/AXI_XADC_CORE_I/XADC_INST belongs to a shape with reference instance JXADC_P_IBUF[0]_inst. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. [**/Nexys4_Master.xdc:337]
Resolution: Verify the location constraints for differential ports are correctly specified in your constraints. The Site type should be of form: IO_LxxP for P-side, and IO_LxxN for N-side (Neg Diff Pair)

 Can anyone explain to me what location restraints the resolution is referring to or what documentation I should look at to get a better understanding of this?

 

Thanks

0 Kudos
1 Reply
Teacher muzaffer
Teacher
7,428 Views
Registered: ‎03-31-2012

Re: What IO standard is necessary to use JXADC port on Nexys 4 Board?

xadc pins are dedicated (when they're used as analog inputs) so you don't need to do anything in synthesis to use these pins. If they are connected on the pcb from the connector to the right pins on the fpga, that's all that's necessary and all you have to do is to configure the xadc block to sample the right vaux pin to be selected to be sample.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos