UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer mnanoop2014
Observer
70 Views
Registered: ‎10-29-2018

Zynq Ultrascale+ ZCU102 embedded design Tutorial (UG1209) petalinux build failure

Hi all, I've been following the UG1209 Embedded design tutorial for Zynq Ultrascale+ (ZCU102 Evaluation board) (link). 

Using Ubuntu 16.04 (not Virtual) with 16 core Intel Xeon, 64GB RAM. Vivado 2018.2 and Petalinux 2018.2.

I am able to generate the HDF file for just the zynq processor in the design and build linux images successfully for it.

But when I also add AXI timers, GPIOs and generate HDF successfully and then try to build new Linux in Petalinux the following way:

petalinux-create -t project -s <proper BSP>
petalinux-config --get-hw-description=<path to new HDF>
(select SD card and save config)
petalinux-build

It fails to build PMU f/w or FSBL. The build log says errors in files in <include> folder for FSBL and PMU f/w and when I check that, I realized those header files are not copied fully or are not copied at all. Some files have missing #endif and some files have missing declarations. I verified with the corresponding files of the earlier Linux build and they have all the files in full.

I tried redownloading BSP packages from Xilinx, tried different BSP packages, tried regenerating HDF again, tried with Petalinux 2017 and the issue remains. 

Am I going wrong anywhere/missing something? Any help would be appreciated.
TIA
Anoop

0 Kudos