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Mentor
Mentor
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Registered: ‎10-07-2011

7-Series: Multiple boot images in SPI/QSPI/BPI PROM

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Hi folks,

Using 2019.2 on Win10x64. The design is targeting an Artix-7 part embedding a Microblaze and has a PCIe link to an external CPU that is connected to the internet. I'm looking for a way for the external CPU to store updated bitstream into the PROM, such that the FPGA gets an updated configuration at next start-up.

The A7 doesn't support PCIe tandem configuration so I have to find something else. Is there a more or less standard way of achieving this?

Otherwise, I was thinking to the following:

  1. The external CPU receives the updated configuration file from the internet and transfers it to FPGA through PCIe
  2. PCIe stores the new image into DDR
  3. Microblaze retrieves new image fro DDR and writes it to the SPI/QSPI/BPI flash
  4. Microblaze tweaks something such that the updated image is used the next time the FPGA is configured (how to do this safely?)

Any hint?

Great thanks!

Claude

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Registered: ‎01-22-2015

@chevalier 

-adding a little to answer of iguo: 

XAPP1247 is for 7-Series as XAPP1257 is for UltraScale. 

If your 7-Series FPGA is using Master SPI configuration mode then after configuration you can access all connections between the FPGA and the flash as ordinary I/O except the clock connection to flash.  The clock connection to flash must be accessed via the STARTUPE2 primitive (see ug953).  With these connections, you can read/write the flash.

We do this with HDL (VHDL) in a Kintex-7.  I have not used the MicroBlaze Processor, but I understand it is implemented using programmable logic (PL).  So, if MicroBlaze can access the STARTUPE2 primitive and all the IO pins of the FPGA then MicroBlaze can read/write flash after FPGA configuration.

When learning about Multiboot for the FPGA be sure to read about barrier images in Appendix-A in XAPP1247.  Barrier images help ensure fallback to the Golden Image when the Update Image that you write to flash is corrupted.

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

Hi,

1. A7 supports Tandem. Guess you looked at pg213? You should check pg054.

2. Other than Tandem, you can develope your own way to deliever the new parial bit by PCAP; but this is exactly what Tandem makes use of. So ignore this.

3. Your steps look good. At step 4 you asked how to do that safely, well, if your design finishes current work and be ready for the next boot, nothing to worry about. You can just trigger PROG_B to start the next configuration. The reason is that here you are doing Re-Configuration, not partial dynamic reconfig, so no extra care is needed here.

5. If your flash is big enough, check 'MultiBoot' in UG470 and see if it's a better (simplier) solution for your project.

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Mentor
Mentor
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Registered: ‎10-07-2011

Hello @iguo 

Tandem (bullet 1 and2 of your reply): I meant the xdma IP is not allowing us to enable tandem configuration for a 7-serie device. So, tandem is usable but the design has to be changed significantly.

Thanks for your comments in 3 and 5. In the mean time, we found xapp1280 "UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3" which is EXACTLY what I tried to describe in my original post. But this is for UltraScale and STARTUPE3. Do you think this will work for 7-Series STARTUPE2? According to that post, I guess it should.

So basically, I would like to make sure that once the FPGA is configured, the xSPI/BPI flash can be mapped to the Microblaze address space and read from/written to by the Microblaze. So, the flash is used for FPGA configuration at start-up and as a normal Microblaze peripheral once the FPGA is configured and running.

Makes sense?

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Registered: ‎01-22-2015

@chevalier 

-adding a little to answer of iguo: 

XAPP1247 is for 7-Series as XAPP1257 is for UltraScale. 

If your 7-Series FPGA is using Master SPI configuration mode then after configuration you can access all connections between the FPGA and the flash as ordinary I/O except the clock connection to flash.  The clock connection to flash must be accessed via the STARTUPE2 primitive (see ug953).  With these connections, you can read/write the flash.

We do this with HDL (VHDL) in a Kintex-7.  I have not used the MicroBlaze Processor, but I understand it is implemented using programmable logic (PL).  So, if MicroBlaze can access the STARTUPE2 primitive and all the IO pins of the FPGA then MicroBlaze can read/write flash after FPGA configuration.

When learning about Multiboot for the FPGA be sure to read about barrier images in Appendix-A in XAPP1247.  Barrier images help ensure fallback to the Golden Image when the Update Image that you write to flash is corrupted.

Mark

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Xilinx Employee
Xilinx Employee
470 Views
Registered: ‎08-10-2008

1. Yes Startupe2 works for 7 series in the same way. Just search for the articles regarding Startupe2 as there are some tiny tips such as https://www.xilinx.com/support/answers/52626.html. Make sure you understand how it works. 

2. Yes it makes sense. Actually a very common usage scenario.

 

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Mentor
Mentor
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Registered: ‎10-07-2011

@iguo markg@prosensing.com 

Thanks folks! I guess I'm all set.

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