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Contributor
Contributor
470 Views
Registered: ‎02-16-2018

AXI Quad SPI serial line status during software reset

Hi,

 

I have something to ask on AXI Quad SPI

In AXI Quad SPI If we do software reset what would be the status of serial lines whether those are tri-stated or what? 

whether is it necessary to do software reset for every new transaction in Standard mode?

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2 Replies
Contributor
Contributor
445 Views
Registered: ‎02-16-2018

Re: AXI Quad SPI serial line status during software reset

sorry for the mistake..

 

whether is it necessary to do DTR and DRR resets for every new transaction in Standard mode?

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Xilinx Employee
Xilinx Employee
421 Views
Registered: ‎10-30-2017

Re: AXI Quad SPI serial line status during software reset

Hi i@007,

 

Please see the below 

DTR_FIFO.PNG

It is clear that DTR should be in reset state before filling any data into the DTR FIFO.

 

Best Regards,
Srikanth
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