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Visitor jorgetonfat
Visitor
10,640 Views
Registered: ‎09-29-2014

Artix-7 Readback through JTAG

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Hi!,

I am using a embeeded microprocessor to configure and readback an Artix-7 FPGA.

I would like to know if it is possible to read the configuration memory through JTAG without issuing the SHUTDOWN command, keeping the FPGA active.

 

I am using now the following sequence of commands but  it is not working:

 

uint32_t CMDS_TO_CONF[17] = {
                0xFFFFFFFF, // dummy
                0xAA995566, // sync
                0x20000000, // noop
                0x30008001, // write to CMD
                0x00000007, // RCRC (reset CRC)
                0x20000000, // noop
                0x20000000, // noop
                0x30008001, // write to CMD
                0x00000004, // RCFG (read configuration)
                0x30002001, // write to FAR
                0x00000000, // frame address to read
                0x20000000, // noop
                0x20000000, // noop
                0x28006000, // type 1 Read 0 Words from FDRO
                0x480E963D, // type 2 Read 955965 Words from  FDRO
                0xFFFFFFFF, // dummy
                0xFFFFFFFF  // dummy
    };

 

 

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Scholar austin
Scholar
20,722 Views
Registered: ‎02-27-2008

Re: Artix-7 Readback through JTAG

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j,

 

Readback while operating can lead to errors, as the BRAM have two ports (not three) so reading them may cause a disturb (change a bit if it being read or written on the same port and address at the same time which is inevitable).

 

Stopping the clocks is all that is required.  Or, not reading the BRAM frames also works.

 

Look at the SEM IP core.  It may already do everything you require (insures the bitstream has 0 errors).

Austin Lesea
Principal Engineer
Xilinx San Jose

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2 Replies
Scholar austin
Scholar
20,723 Views
Registered: ‎02-27-2008

Re: Artix-7 Readback through JTAG

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j,

 

Readback while operating can lead to errors, as the BRAM have two ports (not three) so reading them may cause a disturb (change a bit if it being read or written on the same port and address at the same time which is inevitable).

 

Stopping the clocks is all that is required.  Or, not reading the BRAM frames also works.

 

Look at the SEM IP core.  It may already do everything you require (insures the bitstream has 0 errors).

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Visitor jorgetonfat
Visitor
10,467 Views
Registered: ‎09-29-2014

Re: Artix-7 Readback through JTAG

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Hi Austin,

 

Thank you for your advice!

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