03-27-2018 02:23 AM
When I read CRC configuration register (address 0x0) via ICAPE2 primitive, I always get back 0x0.
Since reading of other registers returns plausible data, there has to be a specific problem with CRC register.
Which settings do I need to get this data filled with CRC of bitstream?
Currently I use:
set_property POST_CRC ENABLE [current_design]
set_property POST_CRC_FREQ 50 [current_design]
set_property POST_CRC_SOURCE PRE_COMPUTED [current_design]
set_property POST_CRC_ACTION HALT [current_design]
set_property POST_CRC_INIT_FLAG DISABLE [current_design]
03-29-2018 04:34 AM
Thanks, but CRC had already been enabled.
Therefore it has to be another setting or the CRC configuration register read content depends on other register contents, for instance FAR.
04-04-2018 12:04 AM
CRC reg has no direct relationship with POST_CRC function. Please read ug470 to understand what RBCRC is. CRC reg is used to store the CRC-32 value during bit downloading.