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Visitor
Visitor
964 Views
Registered: ‎03-22-2018

Artix7 CRC configuration register content

When I read CRC configuration register (address 0x0) via ICAPE2 primitive, I always get back 0x0.
Since reading of other registers returns plausible data, there has to be a specific problem with CRC register.

Which settings do I need to get this data filled with CRC of bitstream?
Currently I use: 
set_property POST_CRC ENABLE [current_design]
set_property POST_CRC_FREQ 50 [current_design]
set_property POST_CRC_SOURCE PRE_COMPUTED [current_design]
set_property POST_CRC_ACTION HALT [current_design]
set_property POST_CRC_INIT_FLAG DISABLE [current_design]


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Moderator
Moderator
919 Views
Registered: ‎01-15-2008

can you set the following in case you have not set

 

set_property  BITSTREAM.GENERAL.CRC ENABLE [current_design]

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Visitor
Visitor
911 Views
Registered: ‎03-22-2018

Thanks, but CRC had already been enabled.
Therefore it has to be another setting or the CRC configuration register read content depends on other register contents, for instance FAR.

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Xilinx Employee
Xilinx Employee
866 Views
Registered: ‎08-10-2008

CRC reg has no direct relationship with POST_CRC function. Please read ug470 to understand what RBCRC is. CRC reg is used to store the CRC-32 value during bit downloading.

 

Thanks,

Ivy

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