cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
860 Views
Registered: ‎03-14-2016

Bitstream writes same frame twice with different data

Hello,

 

in the course of my (extremely protracted) master thesis, I'm dealing with partial reconfiguration.

When I had a closer look on partial bitstreams, i noticed that the same frames are written twice with different data and I'm very eager to know the reason for that.

My best guess would be that the first write operation "blanks" parts of the partition, so that no logic elements drive the same (interconnect) signals. If I remember correctly, there is a statement in the configuration user guide, that there is a global signal that puts the interconnect into high-z state, but this can't be used for partial reconfiguration. Are these assumptions correct?

I'm not sure if anybody can answer the above questions, but what interests me even more is if I can just remove the first write operation from the bitstream and thus reduce its size. It doesn't make sense to me that this first write operation is in there unintentionally, but could the removal cause any electrical problems or even damage the FPGA?

 

Thank you very much,

Markus

0 Kudos
2 Replies
Highlighted
Observer
Observer
771 Views
Registered: ‎03-14-2016

After some research, I found the following statement in UG909, p.96:

"Advisories had been given for prior versions of Vivado software recommending the use of blanking bitstreams for 7 series and Zynq devices to avoid potential glitching conditions. Starting with Vivado 2016.1, these rare glitching scenarios are automatically avoided by embedding specific blanking events in each partial bitstream. Blanking bitstreams, while still available to remove logic from a Reconfigurable Partition, are no longer required to avoid any potential glitch events."

This pretty much answers my first two questions. But what still remains is the question, if removing these blanking frames could cause damage to the device?
When I download a partial bitstream, that was created with Vivado 2017.4 (so it includes the embedded blanking events), the states of registers within the partition changes and also signals that are routed outside of the partition are glitching. That is also why it is recommended to use decoupling at the partition's boundaries.

But which kind of glitches are then avoided by the embedded blanking? Glitches to Block-RAMs? And what about distributed RAMs?
Questions over questions :D

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
749 Views
Registered: ‎08-10-2008

Hi J,
If you are caring about the bit size please use compression. You cannot remove teh blanking or clearing (for US parts) writes.
From previous customers' applications, we found that for some corner usage cases, glitches could happen (not remember what kind of glitch). So blanking and clearing bits are developed for customer's design safe purpose. No damage to device, just function abnormal.

To use Partial please never try to modify the bits yourself, always follow our guidance. In extreme scenario, the device might be damaged if you modify bit manually.

Thanks,
Ivy
------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------