I am attempting to run a boundary scan interconnect test between two FPGAs (Spartan 6). However, there are LVDS buffers for some signals. Is there a way to provide stimulus/measure response of an LVDS signal using JTAG?
AR#6664 states that a post-configuration BSDL file must be used for differential I/Os. I used BSDLANNO to generate a post-configuration BSDL, but the pins that I have defined as differential outputs are unchanged. Is the BSDL file supposed to indicate which pads are differential?