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Newbie
Newbie
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Registered: ‎04-10-2018

Boundary Scanning Spartan 6 - LVDS

Hello all,

I am attempting to run a boundary scan interconnect test between two FPGAs (Spartan 6). However, there are LVDS buffers for some signals. Is there a way to provide stimulus/measure response of an LVDS signal using JTAG? 

 

AR#6664 states that a post-configuration BSDL file must be used for differential I/Os. I used BSDLANNO to generate a post-configuration BSDL, but the pins that I have defined as differential outputs are unchanged. Is the BSDL file supposed to indicate which pads are differential?

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Teacher
Teacher
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Registered: ‎07-09-2009

can you test without configuring the fpga ?

 

the lvds lines, if they are just between the fpga's, 

   could be tested single ended, 

 

if you have external lvds term resistors, good jtag sw copes with that,

    if you are only using internal termination, then even easier.

 

to use differential lvds in jtag, you need to look for 1149.6 support and the separate section in the bsdl file.

 

 

 

 

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