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Observer
Observer
1,003 Views
Registered: ‎06-15-2018

Boundary scan for Kintex-7 ( Help to a newbie)

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Hi All,

I'm new to FPGA's. I'm looking for detailed information about executing boundary scan on my Kintex-7 Ultrascale board. I've searched 2 days for a complete info but could'nt find any good source. Consider that I'm still leraning about FPGA's I don't know where to look anymore. In Xilinx documents I've found BSDL files and such but I don't know hot to use them. Is there any verilog design example with detailed explanations for this matter. I'm lost in the large chunks of data and user guides. Help please. 

 

Thank you all in advance.

Have good day/night.

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Observer
Observer
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Registered: ‎06-15-2018
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Advisor
Advisor
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Registered: ‎04-26-2015

I'm not totally clear on what you're trying to do. Running a boundary scan on any of the Xilinx development boards is trivial: plug a USB cable into the USB-JTAG port on the board, set jumpers/switches to enable JTAG (according to the board user manual), then run Vivado Hardware Manager and click the "Open target" button. Vivado should automatically detect the connected device, assuming that drivers are installed. No need to use BSDL files (they're built-in).

 

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Voyager
Voyager
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Registered: ‎08-16-2018

Boundary scan is nothing but what JTAG does. Maybe not strictly correct, but to be honest, you don't need to bother about that.

Write your HDL, synthesize it, generate your bitstreams and either download them to your device or create a configuration file for your flash.

That last operation will be done with the programming cable, using JTAG. That's probably all you need to know about it for a while.

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Observer
Observer
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Registered: ‎06-15-2018

Thank you for answers. But I need a verilog implementation guide too. For doing scan internally. vithout using vivado's device manager.

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Observer
Observer
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Registered: ‎06-15-2018
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