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Explorer
Explorer
488 Views
Registered: ‎05-14-2017

CFGBVS signal during configuration

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The "CFGBVS"  seem to be a requirement during configuration as is specify in two places.

1) There is a CFGBVS pin in Bank0 that can be tie either to gnd or vcco. If we tie this to gnd, does this represent all my configuration signal to Bank0 should be in the 1.8v range?

2) But then the CFGBVS is also required in the xdc file when we declared it with set property as follow:

"set property CFGBVS GND [current design]"

my question is, if I already tie this to gnd at the fpga pin "cfgbvs" then is it necessary to declare this in the xdc file?

In addition, what if the user makes a mistake and tie the pin to ground and declare it as vcco in the xdc file then which one would take precedent?

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Moderator
Moderator
418 Views
Registered: ‎06-05-2013

Re: CFGBVS signal during configuration

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Declaring the CFGBVS in xdc will let the drc tool know that CFGBVS is set to x value and according it will run the DRC check on the I/O. Here is the AR https://www.xilinx.com/support/answers/55660.html
If don't declare it in the xdc then you might get a warning message & Vivado might not run the equivalent DRC checks.

Hope it helps.
Thanks
Harshit
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466 Views
Registered: ‎01-22-2015

Re: CFGBVS signal during configuration

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@tchin123 

Caution: doing the wrong thing with the CFGBVS pin can damage your FPGA. My answers assume you are using a 7-Series FPGA. If you are not using a 7-Series FPGA then you should carefully read about CFGBVS in the Configuration Guide for specific FPGA.

   There is a CFGBVS pin in Bank0 that can be tie either to gnd or vcco. If we tie this to gnd, does this represent all my configuration signal to Bank0 should be in the 1.8v range?
For 7-Series FPGAs, Table 2-5 of UG470 gives a nice clear answer and says “Caution! When CFGBVS is set to Low for 1.8V/1.5V I/O operation, the VCCO_0 and I/O signals to bank 0 must be 1.8V (or lower). VCCO_14 and VCCO_15 must also be 1.8V/1.5V if configuration I/O in those banks are used during configuration.  Otherwise, the device can be damaged from the application of voltages to pins on these banks that are greater than the 1.8V operation maximum.”

     I already tie this to gnd at the fpga pin "cfgbvs" then is it necessary to declare this in the xdc file?
Yes. In your XDC file you should have constraints that look like the following. According to UG912, DRC checks look at your XDC constraints for CFGBVS and for CONFIG_VOLTAGE to determine if the configuration mode/interface (eg. SPIx1) specified in your constraint for CONFIG_MODE is compatible.

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CONFIG_MODE SPIx1 [current_design]

For 7-Series FPGAs, Tables 2-6, 2-7, and 2-8 in UG470 show you what configuration modes/interfaces you can use when CFGBVS=GND.

     what if the user makes a mistake and tie the pin to ground and declare it as vcco in the xdc file then which one would take precedent?
The physical connection to the CFGBVS pin is the most important.  If you make the wrong physical connection to CFGBVS then the FPGA will probably be damaged.

However, the JTAG interface with the FPGA also uses pins found in FPGA bank-0. Thus, the Xilinx programming cable needs to know the CFGBVS setting so that proper voltage levels are used on the JTAG interface.  I suspect that the Xilinx programming cable gets the CFGBVS setting from your XDC constraints – so, your XDC constraints are important too. 

The Xilinx documentation is not clear what happens if you specify the wrong CFGBVS setting in your XDC constraints. -perhaps the JTAG interface to the FPGA is damaged?  Maybe someone from Xilinx can help us with this question?

Cheers,
Mark

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Registered: ‎01-22-2015

Re: CFGBVS signal during configuration

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@tchin123 

    ...if you specify the wrong CFGBVS setting in your XDC constraints. -perhaps the JTAG interface to the FPGA is damaged?
No. I find from the datasheet, DS593, for the Xilinx programming cable that the output drive voltage depends directly on the voltage that you connect to the Vref pin of the programmer.  So, to prevent damage to the FPGA during configuration, you must do the following:

  • ensure that the CFGBVS pin of the FPGA is connected properly – as I described in previous post
  • ensure that the Vref pin used by the Xilinx programmer cable is connected to VCCO_0

Platform_Cable_USB_II.jpg

Vdrive_vs_Vref_DS593.jpg

Explorer
Explorer
436 Views
Registered: ‎05-14-2017

Re: CFGBVS signal during configuration

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Ok, thanks for the information on correct connection of the CFGBVS pin and VREF on the JTAG connection.

If that is the case then it seem like setting the CFGBVS property in the xdc file is a redundancy, does this make sense? Could this be for something else?

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Moderator
Moderator
419 Views
Registered: ‎06-05-2013

Re: CFGBVS signal during configuration

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Declaring the CFGBVS in xdc will let the drc tool know that CFGBVS is set to x value and according it will run the DRC check on the I/O. Here is the AR https://www.xilinx.com/support/answers/55660.html
If don't declare it in the xdc then you might get a warning message & Vivado might not run the equivalent DRC checks.

Hope it helps.
Thanks
Harshit
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View solution in original post

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