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384 Views
Registered: ‎06-09-2015

Can we connect user logic to dedicated configuration pins like CCLK_0 and DIN_0 in Virtex 6 FPGAs?

 
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Re: Can we connect user logic to dedicated configuration pins like CCLK_0 and DIN_0 in Virtex 6 FPGAs?

Hi muralikrishna.m@coreel.com

Check for STARTUP_VIRTEX6 primitive in UG360 (v3.9) and UG623 (v14.7); I believe with this primitive you can access CCLK pin from the FPGA fabric.

 

Regards,
Bhushan

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